196
Sequence Output Instructions Section 3-4
Variations
Note Immediate refreshing is not supported by CS1D CPU Units.
Note Immediate refreshing is not supported by CS1D CPU Units.
Applicable Program Areas
Operand Specifications
Variations Executed Each Cycle for ON Condition SET
Executed Once for Upward Differentiation @SET
Executed Once for Downward Differentiation %SET
Immediate Refreshing Specification (See note.) !SET
Combined
variations
Executed Once and Bit Refreshed
Immediately for Upward Differentiation (See
note.)
!@SET
Executed Once and Bit Refreshed
Immediately for Downward Differentiation
(See note.)
!%SET
Variations Executed Each Cycle for ON Condition RSET
Executed Once for Upward Differentiation @RSET
Executed Once for Downward Differentiation %RSET
Immediate Refreshing Specification (See note.) !RSET
Combined
Variations
Immediate Refreshing Once for Upward
Differentiation (See note.)
!@RSET
Immediate Refreshing Once for Downward
Differentiation (See note.)
!%RSET
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Area B
CIO Area CIO 000000 to CIO 614315
Work Area W00000 to W51115
Holding Bit Area H00000 to H51115
Auxiliary Bit Area A44800 to A95915
Timer Area ---
Counter Area ---
DM Area ---
EM Area without bank ---
EM Area with bank ---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to ,–(– –) IR15
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