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Data Shift Instructions Section 3-9
Description When the execution condition on the shift input changes from OFF to ON, all
the data from St to E is shifted to the left by one bit (from the rightmost bit to
the leftmost bit), and the ON/OFF status of the data input is placed in the
rightmost bit.
Flags
Precautions The results will not be predictable if two SFT(010) instructions are used with
overlapping shift registers. All words in the range ST to E must be used in only
one SFT(010) instruction.
The bit data shifted out of the shift register is discarded.
When the reset input turns ON, all bits in the shift register from the rightmost
designated word (St) to the leftmost designated word (E) will be reset (i.e., set
to 0). The reset input takes priority over other inputs.
St must be less than or equal to E, but even when St is set to greater than E
an error will not occur and one word of data in St will be shifted.
When St and E are designated indirectly using index registers and the actual
addresses in I/O memory are not within memory areas for data, an error will
occur and the Error Flag will turn ON.
Examples Shift Register Exceeding 16 Bits
The following example shows a 48-bit shift register using words CIO 0128 to
CIO 0130. A 1-s clock pulse is used so that the execution condition produced
by CIO 000005 is shifted into a 3-word register between CIO 012800 and
CIO 013015 every second.
3-9-2 REVERSIBLE SHIFT REGISTER: SFTR(084)
Purpose Creates a shift register that shifts data to either the right or the left.
E
Status of data input
for each shift input
Lost
St+1, St+2, ... St
Name Label Operation
Error Flag ER ON if the indirect IR address for St and E is not in the CIO,
AR, HR, or WR data areas.
OFF in all other cases.
E: CIO 0130 CIO 0129 CIO 0128
(1-s clock)
Reset
Shift input
Data input
Lost
Contents of
CIO 000005
St+1: St:
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