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Timer and Counter Instructions Section 3-6
Description The counter PV is decremented by 1 every time that the count input goes from
OFF to ON. The Completion Flag is turned ON when the PV reaches 0.
Once the Completion Flag is turned ON, reset the counter by turning the reset
input ON or by using the CNR(545)/CNRX(547) instruction. Otherwise, the
counter cannot be restarted.
The counter is reset and the count input is ignored when the reset input is ON.
(When a counter is reset, its PV is reset to the SV and the Completion Flag is
turned OFF.)
Flags
Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these are turned OFF.
Indirect DM/EM
addresses in
binary
--- @ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in
BCD
--- *D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants --- BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers --- DR0 to DR15
Index Registers --- ---
Indirect address-
ing using Index
Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
Area N S
SV
Count input
Counter PV
Reset input
Completion
Flag
Name Label Operation
Error Flag ER ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the address of
a counter Completion Flag or counter PV.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Equals Flag = Unchanged (See note.)
Negative Flag N Unchanged (See note.)
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