Bit 15
Invalid processor configuration. This bit is set if the last PROC command called for an
illegal combination of parameters. The possible causes are:
• Spectrum size greater than 128 or less than 4
• More than 342 bins/slave in FFT modes
• (bins/slave) x (4 + sample size) exceeds 26200 in FFT modes
• (bins/slave) x (sample size) exceeds 3000 for Time Series or Spectra output
• Odd number of bins selected during fast polarization switching
• Bad combination of polarization parameters
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Immediate Status Word #1 (Current State of Affairs) | Output 10
|----------------------------------------------------------------|
Bit 0
No trigger, or, more than 50 ms since last trigger.
Bit 1
Error in loading trigger angle table. See 8.16 Load Antenna Synchronization Table
(LSYNC) (page 297).
Bit 2
PWINFO command is disabled.
Bit 3
Angle sync input is BCD (Else binary angle)
Bit 4
Angle sync is on elevation axis (Else azimuth axis)
Bit 5
Angle sync is enabled
Bit 6
Angle sync allows short output rays
Bit 7
Angle sync is dynamic (else rays begin on sync angles).
Bit 8
DSP has full IAGC hardware and firmware configuration
Bit 9
DSP supports 16-bit floating time series
Bit 11, 10
Current unfolding mode
Bit 13, 12
Number of RVP900/PROC compute processes minus one
Bit 14
DSP supports Power Spectrum output
RVP900 User Guide M211322EN-J
276
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