Vaisala RVP900 - Page 280

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Trigger Count (Low 16-bits) | Output 14
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Trigger Count (high 8-bits) | Output 15
|----------------------------------------------------------------|
The trigger count is a running tally of the number of triggers received by the RVP900 on the
TRIGIN line. It is a full 24-bit counter.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Number of Properly Acquired Bins for Current Range Mask & PRT | Output 16
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| No. of Valid Bins in Initial Part of Ray From Last PROC Cmd | Output 17
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Immediate Status Word #2 (Current State of Affairs) | Output 18
|----------------------------------------------------------------|
Bit 0
Processor supports FFT algorithms
Bit 1
Processor supports Random Phase algorithms
Bit 2
Reserved (zero)
Bit 3
Processor supports DPRT-1 (dual-PRT) algorithms
On dual IFDR systems: Bits 4, 5, 7, and 11 are set if either IFDR fails:
RVP900 User Guide M211322EN-J
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