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Vaisala RVP900 - Pass Auxiliary Arguments to Opcodes (XARGS)

Vaisala RVP900
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Lower AZ (Binary angle) | Input 2
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Upper AZ (Binary angle) | Input 3
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Lower EL (Binary angle) | Input 4
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Upper EL (Binary angle) | Input 5
|----------------------------------------------------------------|
The following arguments specify a trigger period in the same manner as the optional form of
the SETPWF command.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Lower 16–Bits of 32–Bit Trigger Period in Nanoseconds | Input 6
|----------------------------------------------------------------|
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Upper 16–Bits of 32–Bit Trigger Period in Nanoseconds | Input 7
|----------------------------------------------------------------|
RVP900 User Guide M211322EN-J
320

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