Analog Devices adsp-2100 - Page 475

EControl/Status Registers
E – 15
Non-Memory-Mapped Registers
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
11109876543210
SPORT1 Receive or IRQ0
Timer
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
SPORT1 Transmit or IRQ1
IRQ2
INTERRUPT FORCE BITS
INTERRUPT CLEAR BITS
000000000000
SPORT0 Receive
SPORT0 Transmit
IRQ2
SPORT0 Receive
(must be set to 0 for ADSP-2105)
SPORT0 Transmit
(must be set to 0 for ADSP-2105)
(must be set to 0 for ADSP-2105)
(must be set to 0 for ADSP-2105)
IFC (write-only)
IMASK
543210
Timer
SPORT0 Receive (must be set to 0 for ADSP-2105)
000000
SPORT0 Transmit
(must be set to 0 for ADSP-2105)
1 = enable
0 = disable (mask)
INTERRUPT ENABLES
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
IRQ2
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2111