Analog Devices adsp-2100 - Page 477

EControl/Status Registers
E – 17
Non-Memory-Mapped Registers
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
IFC (write-only)
IMASK
11109876543210
Timer
000000000000
IRQ2
15 14 13 12
0000
Timer
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
IRQ2
BDMA Interrupt
INTERRUPT FORCE BITS
INTERRUPT CLEAR BITS
SPORT0 Receive
SPORT0 Transmit
SPORT0 Receive
SPORT0 Transmit
IRQE
BDMA Interrupt
IRQE
543210
000000
76
00
SPORT0 Receive
IRQL0
IRQL1
SPORT0 Transmit
98
00
BDMA Interrupt
IRQE
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
IRQ2
INTERRUPT ENABLES
1 = enable
0 = disable (mask)
ADSP-2181
ADSP-2181