GR740-UM-DS, Nov 2017, Version 1.7 221 www.cobham.com/gaisler
GR740
Table 251.0x08 - Class Code and Revision ID register
31 87 0
Class Code Revision ID
0x0B4000 0x00
rr
31: 8 Class Code, 0x0B4000
7: 0 Revision ID, 0x00
Table 252.0x0C - BIST, Header Type, Latency Timer, and Cache Line Size register
31 24 23 16 15 8 7 0
BIST Header Type Latency Timer Cache Line Size
0
0
00
rrrwrw
31: 24 BIST - NOT IMPLEMENTED, Returns zeros
23: 16 Header Type - Returns 00
15: 8 Latency Timer - All bits are writable
7: 0 Cache Line Size - NOT IMPLEMENTED, Returns zero
Table 253.0x10-0x24 - Base Address Registers
31 43210
Base Address PF Type MS
0
*00
rw r r r
31: 4 Base Address - The size of the BAR is determine by how many of the bits (starting from bit 31) are
implemented. Bits not implemented returns zero.
The first two BARs are 128 MiB in size by default. The third BAR is 8 MiB by default. The 8 MiB
BAR is suitable for mapping registers.
3 Prefetchable (PF) - zero indicating non-prefetchable. The two first BARs have the prefetchable bit
set. The third BAR is not prefetchable and is suitable for mapping system registers.
2: 1 Type - Returns zero.
0 Memory Space Indicator (MS) - Returns zero
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