COBHAM GR740 - Page 447

GR740-UM-DS, Nov 2017, Version 1.7 447 www.cobham.com/gaisler
GR740
39.5.9 Ethernet MDIO timing
The Ethernet MDIO interface is generated synchronously in the system clock domain. The generated
MDC clock frequency is set using a scaler register in the IP core.
Table 586.Timing parameters
Name Parameter Reference edge Min Max Unit
t
MDIO0
MDIO clock-to-output delay rising clk edge where mdc
rises
4
4Tclk
t
MDIO1
MDIO input sampling point rising clk edge where mdc
falls
1
1Tclk
Figure 62. Timing waveforms
eth0_mdio (out)
internal clk
eth0_mdio (in)
t
MDIO0
eth0_mdc
t
MDIO1