COBHAM GR740 - Page 446

GR740-UM-DS, Nov 2017, Version 1.7 446 www.cobham.com/gaisler
GR740
39.5.8 Gigabit Ethernet Media Access Controller (MAC) w. EDCL timing
The timing waveforms and timing parameters are shown in figure 61 and are defined in table 585.
Table 585.Timing parameters
Name Parameter Reference edge Min Max Unit
t
ETHTXCLK0
Ethernet MII transmit clock
(eth*_txclk) period
-
40
-ns
t
ETHRXCLK0
Ethernet MII receive clock (eth*_rx-
clk) period
-
40
3)
-ns
t
ETHGTXCLK0
Ethernet GMII transmit clock
(eth*_gtxclk) period
-
8
-ns
t
ETHRXCLK1
Ethernet GMII receive clock period
(eth*_rxclk)
-
8
3)
-ns
t
ETH0MII
transmitter clock to output delay rising (MII) clock edge
0
1)
30
2)
ns
t
ETH0GMII
transmitter clock to output delay rising (GMII) clock edge 2.58 10.92 ns
t
ETH1MII/
GMII_ETH0
input to receiver clock hold, ETH0
4)
rising RX clock edge 1.84 - ns
t
ETH2MII/
GMII_ETH0
input to receiver clock setup, ETH0
4)
rising RX clock edge 0.9 - ns
t
ETH1MII/
GMII_ETH1
input to receiver clock hold, ETH1
4)
rising RX clock edge 2.53 - ns
t
ETH2MII/
GMII_ETH1
input to receiver clock setup, ETH1
4)
rising RX clock edge 0.69 - ns
1)
This parameter is guaranteed by design and is not tested
2)
This parameter is determined by static timing analysis and is not tested
3)
eth*_rxclk is used in both MII and GMII mode, with different frequencies.
4)
signals col, crs, mdint, mdio are resynchronized internally and do not have any setup/hold timing requirements
Figure 61. Timing waveforms
t
ETH0
eth*_txd/txen/txer
gtx/tx/rx clock
t
ETH0
t
ETH1
t
ETH2
eth*_rxd/rxdv/rxer