COBHAM GR740 - Page 453

GR740-UM-DS, Nov 2017, Version 1.7 453 www.cobham.com/gaisler
GR740
Table 591.Timing parameters - PROM and I/O accesses
Name Parameter Reference edge Min Max Unit
t
FTMCTRL0
address clock to output delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL1
clock to output delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL2
clock to output delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL3
clock to data output delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL4
clock to data non-tri-state delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL5
clock to data tri-state delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL6
clock to output delay
rising clk edge
1)
0
2)
40
3)
ns
t
FTMCTRL7
data input to clock setup
rising clk edge
1)
0
2)
-ns
t
FTMCTRL8
data input from clock hold
rising clk edge
1)
--ns
t
FTMCTRL9
input to clock setup
rising clk edge
1)
0
2)
-ns
t
FTMCTRL10
input from clock hold
rising clk edge
1)
--ns
1)
Timing values are relative to the internal clock for the PROM/IO memory controller.
2) Guaranteed by design, not tested
3) Verified by static timing analysis, not tested
Figure 68. Timing waveforms - I/O accesses
t
FTMCTRL0
promio_addr]
internal sys_clk
t
FTMCTRL1
promio_data[]
(output)
promio_data[]
(input)
io_sn[]
t
FTMCTRL3,
t
FTMCTRL4
promio_oen
promio_wen
t
FTMCTRL9
promio_brdyn
t
FTMCTRL10
t
FTMCTRL2
t
FTMCTRL2
t
FTMCTRL6
t
FTMCTRL6
promio_addr[]
internal sys_clk
io_sn[]
t
FTMCTRL7
t
FTMCTRL8
t
FTMCTRL5
t
FTMCTRL1