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COBHAM GR740 User Manual
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GR740-UM-DS, Nov 2017, Version 1.7
452
www.cobham.com/gaisler
GR740
39.5.14
Fault-tolerant 8/16-bit
PROM/IO memory
interface timing
The timing waveforms and timing parameters are show
n in figures 67 and 68
, and are defined in table
591.
Figur
e 67.
T
iming waveforms
- PROM accesses
t
FTMCTRL0
promio_addr[]
internal sys_clk
t
FTMCTRL1
promio_data[]
(output)
promio_data[]
(input)
prom_cen[]
t
FTMCTRL3,
t
FTMCTRL4
promio_oen
promio_we
n
t
FTMCTRL9
promio_brdyn
t
FTMCTRL10
t
FTMCTRL2
t
FTMCTR
L2
t
FTMCTRL6
t
FTMCTR
L6
promio_addr[]
internal sys_clk
prom_cen[]
t
FTMCTRL7
t
FTMCTRL8
t
FTMCTR
L5
t
FTMCTRL1
451
453
Table of Contents
Default Chapter
2
Table of Contents
2
1 Introduction
8
Scope
8
Preliminary Data Sheet Limitations
8
Updates and Feedback
8
Software Support
8
Development Board
8
Performance, Power Consumption and Radiation Tolerance
8
Reference Documents
9
Document Revision History
10
Acronyms
13
Definitions
14
Register Descriptions
15
2 Architecture
16
Overview
16
Cores
18
Memory Map
19
Interrupts
22
Plug & Play and Bus Index Information
22
3 Signals
27
Bootstrap Signals
27
Configuration for Flight
28
Pin Multiplexing
28
Complete Signal List
32
Pin Driver Configuration
35
4 Clocking and Reset
36
Clock Inputs
36
Clock Loop for SDRAM
36
Reset Scheme
37
Clock Multiplexing for Main System Clock, SDRAM and Spacewire
38
PLL Control and Configuration
39
PLL Watchdog
40
PCI Clock
40
MIL-STD-1553B Clock
40
Clock Gating Unit
40
Debug AHB Bus Clocking
41
Notes on Ethernet Interface Clock and Mode Switch
41
5 Technical Notes
42
GRLIB AMBA Plug&Play Scanning
42
Processor Register File Initialisation and Data Scrubbing
42
PROM-Less Systems and Spacewire RMAP
42
System Integrity and Debug Communication Links
43
Separation and ASMP Configurations
43
Clock Gating
44
Software Portability
45
Level-2 Cache
45
Time Synchronisation
46
Bridges, Posted-Writes and ERROR Response Propagation
47
6 LEON4 - Fault-Tolerant High-Performance SPARC V8 32-Bit Processor
48
Overview
48
LEON4 Integer Unit
50
Cache System
56
Memory Management Unit
59
Floating-Point Unit
60
Co-Processor Interface
61
AMBA Interface
61
Multi-Processor System Support
63
ASI Assignments
64
Configuration Registers
69
Software Considerations
78
7 Floating-Point Control Unit
80
Floating-Point Register File
80
Floating-Point State Register (FSR)
80
Floating-Point Exceptions and Floating-Point Deferred-Queue
80
8 High-Performance IEEE-754 Floating-Point Unit
82
Overview
82
Functional Description
82
9 Level 2 Cache Controller
86
Overview
86
Operation
86
Operation
89
Registers
92
10 SDRAM Memory Controller with Reed-Solomon EDAC
100
Overview
100
Operation
100
Limitations
100
SDRAM Back-End Operation
101
Fault-Tolerant Operation
104
Registers
107
Sdram Configuration Register
108
11 Memory Scrubber and AHB Status Register
112
Overview
112
Operation
112
Registers
115
Configuration Register
118
12 IOMMU - Bridge Connecting Master I/O AHB Bus
121
Overview
121
Bridge Operation
121
General Access Protection and Address Translation
124
Access Protection Vector
125
IO Memory Management Unit (IOMMU) Functionality
127
Fault-Tolerance
130
Statistics
131
ASMP Support
131
Registers
132
Interrupt Mask Register
137
13 Spacewire Router
142
Overview
142
Operation
142
Spacewire Ports
152
AMBA Ports
154
Configuration Port
177
14 Gigabit Ethernet Media Access Controller (MAC)
204
Overview
204
Operation
204
Tx DMA Interface
205
Rx DMA Interface
207
MDIO Interface
210
Ethernet Debug Communication Link (EDCL)
210
Media Independent Interfaces
212
Registers
213
32 Bit PCI/AHB Bridge
218
Overview
218
Configuration
218
Operation
224
PCI Initiator Interface
227
PCI Target Interface
228
DMA Controller
229
PCI Trace Buffer
232
Interrupts
232
Reset
233
15.10 Registers
233
16 MIL-STD-1553B / AS15531 Interface
241
Overview
241
Electrical Interface
241
Operation
242
Bus Controller Operation
243
Remote Terminal Operation
248
Event Log
250
Bus Monitor Operation
252
Clocking and Reset
252
Registers
253
17 CAN 2.0 Controllers with DMA
263
Overview
263
Interface
264
Protocol
264
Status and Monitoring
264
Transmission
264
Reception
267
Global Reset and Enable
270
Interrupt
270
Registers
271
17.10 Memory Mapping
281
18 Bridge Connecting Slave I/O AHB Bus to Processor AHB Bus
282
Overview
282
Operation
282
Registers
285
19 Fault-Tolerant 8/16-Bit PROM/IO Memory Interface
286
Overview
286
PROM Access
286
Memory Mapped IO
288
8-Bit and 16-Bit PROM Access
289
8- and 16-Bit I/O Access
290
Burst Cycles
290
Memory EDAC
291
Bus Ready Signalling
291
Registers
293
20 General Purpose Timer Units
297
Overview
297
Operation
297
Registers
298
21 Multiprocessor Interrupt Controller with Extended ASMP Support
301
Overview
301
Operation
301
Registers
306
22 General Purpose I/O Ports
316
Overview
316
Operation
316
Registers
317
23 UART Serial Interfaces
323
Overview
323
Operation
323
Baud-Rate Generation
324
Loop Back Mode
325
FIFO Debug Mode
325
Interrupt Generation
325
Registers
326
24 SPI Controller Supporting Master and Slave Operation
328
Overview
328
Operation
328
Registers
331
25 Clock Gating Unit
338
Overview
338
Operation
338
Registers
339
26 LEON4 Statistics Unit (Performance Counters)
342
Overview
342
Multiple APB Interfaces
344
Registers
345
27 AHB Status Registers
349
Overview
349
Operation
349
Registers
350
28 Register for Bootstrap Signals
351
Overview
351
Operation
351
Registers
351
29 Temperature Sensor Controller
353
Overview
353
Operation
353
Registers
354
30 Register Bank for I/O and PLL Configuration Registers
356
Overview
356
Operation
356
Registers
358
31 Spacewire - Time Distribution Protocol Controller
363
Overview
363
Protocol
363
Functionality
363
Registers
370
32 Bridge Connecting Debug AHB Bus to Processor AHB Bus
385
Overview
385
Operation
385
Registers
388
33 LEON4 Hardware Debug Support Unit
389
Overview
389
Operation
389
AHB Trace Buffer
390
Instruction Trace Buffer
392
DSU Memory Map
393
DSU Registers
395
34 JTAG Debug Link with AHB Master Interface
405
Overview
405
Operation
405
Registers
406
35 Spacewire Debug Link
407
35.2.1 Overview
407
Operation
407
Link Interface
408
Time-Code Distribution
410
Receiver DMA Channels
410
Transmitter DMA Channels
415
Rmap
418
AMBA Interface
422
Registers
423
36 AHB Trace Buffer Tracing Master I/O AHB Bus
429
Overview
429
Operation
429
Registers
431
37 AMBA AHB Controller with Plug&Play Support
435
Overview
435
Operation
435
38 AMBA AHB/APB Bridge with Plug&Play Support
437
Overview
437
Operation
437
39 Electrical Description
438
Absolute Maximum Ratings
438
Recommended DC Operating Conditions
438
Input and Output Signal DC Characteristics
439
Power Supplies
439
AC Characteristics
441
40 Mechanical Description
458
Component and Package
458
Package Placement Diagram
459
Pin Assignment
460
Package Drawing
475
41 Temperature and Thermal Resistance
479
42 Ordering Information
480
43 Silicon Revisions and Errata
481
Overview
481
Change and Errata Descriptions
482
4
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COBHAM GR740 Specifications
General
Brand
COBHAM
Model
GR740
Category
Computer Hardware
Language
English
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