GR740-UM-DS, Nov 2017, Version 1.7 96 www.cobham.com/gaisler
GR740
9.4.6
Table 74. 0x24 - L2CERRA - L2C Error address register
Error address register
9.4.7
Table 75. 0x28 - L2CTCB - L2C TAG-Check-Bits register
TAG check bits register
9.4.8
Table 76. 0x2C - L2CCB - L2C Data-Check-Bits register
Data check bits register
9.4.9
Table 77. 0x30 - L2CSCRUB - L2C Scrub control/status register
Scrub control/status register
31 0
Error Address (EADDR)
NR
r
31: 0 Error Address (EADDR)
31 76 0
RESERVED TCB
00
rrw
31: 7 RESERVED
6: 0 TAG Check-bits (TCB) - Check-bits which can be selected by the “Select check-bit“ field in the
error status/control register for TAG updates
31 28 27 0
RESERVED CB
00
rrw
31: 28 RESERVED
27: 0 Data Check-bits (CB) - Check-bits which can be selected by the “Select check-bit“ field in the error
status/control register for TAG updates
31 16 15 4 3 2 1 0
INDEX RESERVED WAY PE
N
EN
00000
rw r rw rw rw
31: 16 Scrub Index (INDEX) - Index for the next line scrub operation
15: 4 RESERVED
3: 2 Scrub Way (WAY) - Way for the next line scrub operation
1 Scrub Pending (PEN) - Indicates when a line scrub operation is pending. When the scrubber is dis-
abled, writing ‘1’ to this bit scrubs one line.
0 Scrub Enable (EN) - Enables / disables the automatic scrub functionality.
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