14
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
84 DPMS Circuit............................................................................................................................182
85 8-Bit Hub Interface Routing Example .......................................................................................183
86 8-Bit Hub Interface Single HIREF/HI_VSWING Generation Circuit Option A...........................185
87 8-Bit Hub Interface Local HIREF/HI_VSWING Generation Circuit Option B ............................186
88 8-Bit Hub Interface Single HIREF/HI_VSWING Generation Circuit Option C ..........................186
89 8-Bit Hub Interface Local HIREF/HI_VSWING Generation Circuit Option D............................187
90 GMCH Locally Generated Reference Voltage Divider Circuit ..................................................187
91 Individual HLVREF and PSWING Voltage Reference Divider Circuits for GMCH ...................188
92 Serial ATA Trace Spacing Recommendation...........................................................................192
93 SATA BIAS Connections ..........................................................................................................193
94 SATALED# Circuitry Example..................................................................................................193
95 Combination Host-Side/Device-Side IDE Cable Detection.......................................................196
96 Device Side IDE Cable Detection.............................................................................................197
97 Connection Requirements for Primary IDE Connector.............................................................198
98 Connection Requirements for Secondary IDE Connector........................................................199
99 6300ESB AC'97 - Codec Connection.......................................................................................200
100 6300ESB AC'97 – AC_BIT_CLK Topology ..............................................................................201
101 6300ESB AC'97 – AC_SDOUT/AC_SYNC Topology ..............................................................202
102 6300ESB AC'97 – AC_SDIN Topology ....................................................................................202
103 Example Speaker Circuit ..........................................................................................................205
104 CNR Interface...........................................................................................................................207
105 Motherboard AC’97 CNR Implementation with a Single Codec Down On Board.....................208
106 Motherboard AC’97 CNR Implementation without Codec Down On Board..............................209
107 Trace Routing...........................................................................................................................211
108 Recommended General USB Trace Spacing (55 Ω ± 10%).....................................................211
109 USB BIAS Connections............................................................................................................212
110 Good Downstream Power Connection .....................................................................................214
111 A Common-Mode Choke..........................................................................................................215
112 Front Panel Header Schematic ................................................................................................218
113 Motherboard Front Panel USB Support....................................................................................219
114 LPC Interface Diagram.............................................................................................................220
115 LPC Interface Topology............................................................................................................220
116 SMBUS 2.0/SMLink Interface...................................................................................................222
117 High Power/Low Power Mixed VCC_SUSPEND/VCC_CORE Architecture ............................223
118 PCI Bus Layout Example..........................................................................................................225
119 PCI Bus Layout Example with IDSEL.......................................................................................225
120 PCI 33MHz Clock Layout Example ..........................................................................................226
121 Example PIRQ Routing ............................................................................................................227
122 66 MHz PCI-X, Two Slots, Two Down Devices Configuration..................................................229
123 66 MHz PCI-X, One Down Device Configuration .....................................................................229
124 66 MHz PCI-X, Three Slot Configuration..................................................................................230
125 66 MHz Clock Signal Configuration..........................................................................................231
126 Usage Model for SBR Functionality..........................................................................................232
127 RTCX1 and SUSCLK Relationship in 6300ESB.......................................................................233
128 External Circuitry in the 6300ESB Without Use of Internal RTC ..............................................234
129 External Circuitry for the 6300ESB RTC ..................................................................................234
130 Diode Circuit to Connect RTC External Battery........................................................................237
131 RTCRST# External Circuit for the 6300ESB RTC....................................................................238
132 FWH/CPU UP Signal Topology Solution..................................................................................241
133 FWH Level Translation Circuitry...............................................................................................241
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