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Intel 855GME User Manual
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54
In
tel
®
855GME Chi
pset an
d Intel
®
6300ESB ICH Embedde
d P
lat
form Design Guide
In
tel
®
Pen
tium
®
M/Ce
ler
on
®
M Process
or FSB Design and Power
De
livery Guidelines
Ad
dre
ss
Grou
p 1
REQ4#
616
HREQ4
#
276
REQ3#
616
HREQ3
#
383
REQ2#
616
HREQ2
#
247
REQ1#
616
HREQ1
#
378
REQ0#
616
HREQ0
#
569
A16#
616
HA1
6#
491
A1
5#
6
16
HA1
5#
37
5
A1
4#
6
16
HA1
4#
56
2
A1
3#
6
16
HA1
3#
50
1
A1
2#
6
16
HA1
2#
52
2
A1
1#
616
HA1
1#
566
A1
0#
6
16
HA1
0#
56
0
A9
#
6
16
H
A9#
327
A8
#
6
16
H
A8#
333
A7
#
6
16
H
A7#
274
A6
#
6
16
H
A6#
523
A5
#
6
16
H
A5#
551
A4
#
6
16
H
A4#
352
A3
#
6
16
H
A3#
468
ADST
B[0]
#
6
16
HA
DSTB
[0]
#
41
9
T
ab
le 9.
Intel
®
P
en
tiu
m
®
M/Celeron
®
M P
rocessor
and G
M
C
H Sou
rce Synch
ronous
FSB Signal Package Lengths
(Shee
t
5 of 6)
Signal
Group
CPU Signal
Na
me
Intel
®
Penti
um
®
M/Cele
ron
®
M
Pr
oces
sor
Pack
age
Trace Len
gth
(mils
)
GMCH Si
gnal
Name
GMC
H Pack
ag
e T
race
Leng
th (m
ils)
53
55
Table of Contents
Default Chapter
3
Table of Contents
3
Introduction
21
Conventions and Terminology
21
Reference Documents
23
System Overview
25
Terminology
25
System Features
25
Embedded Intel® 855GME Chipset System Block Diagram
26
Component Features
27
Architectural Features
27
Intel ® Pentium ® M Processor
27
Intel ® Pentium ® M Processor on 90 Nm Process with 2 MB L2 Cache
27
Packaging/Power
27
Intel ® Celeron ® M Processor
28
Intel ® Celeron ® M Processor on 90 Nm Process
28
ULV Intel ® Celeron ® M Processor at 600 Mhz
28
Integrated System Memory DRAM Controller
29
Intel ® 855GME Chipset Graphics Memory Controller Hub (82855GME)
29
Intel ® Pentium ® M Processor/Intel ® Celeron ® M Processor Support
29
Internal Graphics Controller
29
Firmware Hub (FWH)
31
Intel ® 6300ESB System Features
31
Packaging/Power
31
Packaging/Power
32
General Design Considerations
33
Nominal Board Stack-Up
33
Recommended Board Stack-Up Dimensions
34
Alternate Stack-Ups
35
4 Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines
37
Intel ® Pentium ® M/Celeron ® M Processor FSB Design and Power Delivery Guidelines
37
Intel ® Pentium ® M/Celeron ® M Processor FSB Design Recommendations
37
Recommended Stack-Up Routing and Spacing Assumptions
37
Trace Space to Trace - Reference Plane Separation Ratio
37
Recommended Stack-Up Calculated Coupling Model
38
Trace Space to Trace Width Ratio
38
Three-To-One Trace Spacing-To-Trace Width Example
38
Signal Propagation Time-To-Distance Relationship and Assumptions
39
Trace Spacing Versus Trace to Reference Plane Example
38
Two-To-One Trace Spacing-To-Trace Width Example
38
Recommended Stack-Up Capacitive Coupling Model
39
Common Clock Signals
40
Common Clock Signal Internal Layer Routing Guidelines
40
Package Length Compensation
41
Source Synchronous Signals General Routing Guidelines
42
Common Clock Topology
42
Signal Package Lengths and Minimum Board Trace Lengths
42
Signals GND Referencing to Layer 5 and Layer 7 Ground Planes
43
Data Signals
44
Source Synchronous Address Signals
45
Signals GND Referencing to Layer 2 and Layer 4 Ground Planes
46
Data Signals
46
Source Synchronous - Data Group
47
Address Signals
47
Source Synchronous - Address Group
48
Trace Length Mismatch Mapping
48
Data Signal Routing Guidelines
48
GMCH (82855GME) FSB Signal Package Lengths
49
Intel ® Pentium ® M/Celeron ® M Processor and Intel ® 855GME Chipset
49
Signal Trace Length Mismatch Mapping
49
Address Signal Routing Guidelines
49
FSB Signal Package Lengths
50
Length Matching Constraints
55
Package Length Compensation
56
Trace Length Equalization Procedures
56
Trace Length Equalization Procedures with Allegro
57
Asynchronous Signals
58
Asynchronous AGTL+ Nets
58
Topology 1A: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - IERR
59
Topology 1B: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - FERR# and THERMTRIP
59
Layout Recommendations for Topology 1A
59
Topology 1C: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - PROCHOT
60
Routing Illustration for Topology 1A
59
Layout Recommendations for Topology 1B
60
Topology 2A: Open Drain (OD) Signals Driven by and Gate-PWRGOOD
61
Routing Illustration for Topology 1B
60
Layout Recommendations for Topology 1C
61
Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK
62
Topology 3: CMOS Signals Driven by 6300ESB to CPU and FWH - INIT
62
Routing Illustration for Topology 1C
61
Routing Illustration for Topology 2A
61
Layout Recommendations for Topology 2A
62
Layout Recommendations for Topology 2B
62
Voltage Translation Logic
63
Pentium ® M/Celeron ® M Processor RESET# Signal
64
Routing Illustration for Topology 2B
62
Processor RESET# Signal Routing Topology with no ITP700FLEX Connector
64
Processor RESET# Routing Example
65
Voltage Translation Circuit
64
Processor RESET# Signal Routing Example with ITP700FLEX Debug Port
65
Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
65
Pentium ® M/Celeron ® M Processor and Intel 855GME
66
Chipset GMCH (82855GME) Host Clock Signals
66
Pentium ® M/Celeron ® M Processor)
66
Routing Recommendations
67
(82855GME) Host Clock Layout Routing Example
67
AGTL+ I/O Buffer Compensation
69
Pentium ® M/Celeron ® M Processor AGTL+ I/O Buffer Compensation
69
Resistive Compensation
70
Primary Side Layout
71
Pentium ® M/Celeron ® M Processor System Bus Strapping
72
Design Recommendations
74
PLL Voltage Design for Low Voltage Intel
74
Pentium ® M
74
Processors on 90 Nm Process with 2 MB L2 Cache
74
Processor RESET# Signal Routing Topology with ITP700FLEX Connector
65
Intel System Validation Debug Support
75
ITP Support
75
Background/Justification
75
Implementation
75
Background/Justification
76
Implementation
76
Pentium ® M/Celeron ® M Processor Logic Analyzer Support (FSB LAI)
76
Intel ® Pentium ® M/Celeron ® M Processor On-Die Logic
76
Analyzer Trigger (ODLAT) Support
76
Onboard Debug Port Routing Guidelines
77
Recommended Onboard ITP700FLEX Implementation
77
ITP Signal Routing Guidelines
77
ITP700FLEX Debug Port Signals
78
Pentium M/Celeron M Processor
80
Recommended ITP700FLEX Signal Terminations
80
ITP Signal Routing Example
81
ITP_CLK Routing to ITP700FLEX Connector
82
ITP700FLEX Design Guidelines for Production Systems
83
Recommended ITP Interposer Debug Port Implementation
84
ITP_CLK Routing to ITP Interposer
84
ITP Interposer Design Guidelines for Production Systems
85
Logic Analyzer Interface (LAI)
85
Electrical Considerations
86
Mechanical Considerations
86
Processor Phase Lock Loop (PLL) Design Guidelines
86
Processor PLL Power Delivery
86
Power Delivery and Decoupling
87
Processor PLL Decoupling Requirements
88
Processor PLL Voltage Supply Power Sequencing
88
Routing Example
88
Thermal Power Dissipation
89
Intel ® Pentium ® M/Celeron ® M Processor Decoupling Recommendations
90
Transient Response
90
High-Frequency/MID-Frequency and Bulk Decoupling Capacitors
91
Processor Core Voltage Plane and Decoupling
91
Intel ® Pentium ® M/Celeron ® M Processor Socket Core Power Delivery Corridor
92
Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery
93
North Corridor' Zoom-In View
99
Processor and GMCH VCCP Voltage Plane and Decoupling
100
GMCH Core Voltage Plane and Decoupling
101
Power and Sleep State Definitions
101
Power Delivery Map
103
Intel 855GME Chipset Platform Power-Up Sequence
105
6300ESB Power Sequencing Requirements
105
GMCH Power Sequencing Requirements
105
V5REF/3.3V Sequencing
105
DDR Memory Power Sequencing Requirements
106
PCI-X Power Sequencing
106
V/1.5V Power Sequencing
106
Intel 855GME Chipset Platform Power Delivery Guidelines
107
GMCH VCCSM Decoupling
108
Intel 855GME Chipset and Decoupling Guidelines
108
Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery and Decoupling Concept Example (Option #4)
93
GMCH Decoupling Recommendations
108
DDR SDRAM VDD Decoupling
109
DDR VTT Decoupling Placement and Layout Guidelines
109
DDR Memory Power Delivery Design Guidelines
109
Power Delivery Guidelines
110
DDR SMRCOMP Resistive Compensation
111
GMCH and DDR SMVREF Design Recommendations
111
DDR SMRCOMP and VTT 1.25 V Supply Disable in S3/Suspend
112
DDR VTT Termination
112
GMCH System Memory Reference Voltage Generation Circuit
112
Other GMCH Reference Voltage and Analog Power Delivery
113
Gmch Gtlvref
113
GMCH AGTL+ I/O Buffer Compensation
115
GMCH AGTL+ Reference Voltage
115
GMCH Analog Power
116
Intel ® 6300ESB Power Delivery
118
Power Supply PS_ON Consideration
119
Intel ® 6300ESB Analog Power Delivery
120
Intel ® 6300ESB Decoupling Recommendations
120
Intel ® 6300ESB Standby Power Distribution
120
Intel® 6300ESB Power Consumption
120
6300ESB Power Signal Decoupling
121
FWH Decoupling
121
Hub Interface Decoupling
121
Thermal Design Power
121
Power Signal Decoupling
121
System Memory Design Guidelines (DDR-SDRAM)
123
Introduction
123
Length Matching and Length Formulas
124
Package Length Compensation
124
Length Matching Formulas
124
Topologies and Routing Guidelines
125
Clock Signals - SCK[5:0], SCK[5:0]
125
Clock Topology Diagram
125
DDR Clock Routing Guidelines
126
DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#)
126
Clock Length Matching Requirements
127
Clock Reference Lengths
128
Clock Length Package Table
130
Data Signals - SDQ[71:0], SDM[8:0], SDQS[8:0]
130
Data Bus Topology
131
Data Signal Routing Topology
131
SDQS to Clock Length Matching Requirements
133
Data to Strobe Length Matching Requirements
134
SDQ to SDQS Mapping
135
SDQ/SDQS Signal Package Lengths
136
Control Signals - SCKE[3:0], SCS[3:0]
138
Control Signal to DIMM Mapping
138
Control Signal Routing Topology
139
Control Signal Routing Guidelines
140
Control to Clock Length Matching Requirements
140
Control Signal to Clock Trace Length Matching Diagram
141
Control Group Package Length Table
142
Command Signals - SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE
142
Command Signal Routing Topology
142
Control Group Package Lengths
142
Command Topology Routing Guidelines
143
Command Topology Length Matching Requirements
144
Command Group Package Length Table
146
CPC Signals - SMA[5,4,2,1], SMAB[5,4,2,1]
146
Command Group Package Lengths
146
Control Signal to DIMM Mapping
146
CPC Signal Routing Topology
147
CPC Control Signal Routing Topology
147
CPC Signal Routing Guidelines
148
CPC to Clock Length Matching Requirements
148
CPC Control Signal Routing Guidelines
148
CPC Group Package Length Table
150
Feedback - RCVENOUT#, RCVENIN
150
ECC Guidelines
150
GMCH ECC Functionality
150
CPC Group Package Lengths
150
DRAM Clock Flexibility
151
Integrated Graphics Display Port
153
Analog RGB/CRT Guidelines
153
Ramdac/Display Interface
153
Reference Resistor (RSET)
153
RAMDAC Board Design Guidelines
154
DAC Routing Guidelines
155
Recommended GMCH DAC Components
156
DAC Power Requirements
157
HSYNC and VSYNC Design Considerations
158
DDC and I C Design Considerations
158
LVDS Transmitter Interface
158
Length Matching Constraints
159
Package Length Compensation
159
LVDS Routing Guidelines
160
Digital Video out Port
161
DVO Interface Signal Groups
162
DVO/I2C to AGP Pin Mapping
162
DVOB and DVOC Port Interface Routing Guidelines
163
Length Mismatch Requirements
163
Package Length Compensation
164
DVOB and DVOC Routing Guidelines
165
Rset Placement
156
DVOB and DVOC Routing Guideline Summary
165
DVOB and DVOC Port Termination
166
DVOB and DVOC Assumptions, Definitions, and Specifications
167
DVOB and DVOC Simulation Method
167
DVOB and DVOC Simulations Model
167
DVOB and DVOC Port Flexible (Modular) Design
168
DVOB and DVOC Module Design
168
Generic Connector Model
169
DVO GMBUS and DDC Interface Considerations
170
Leaving the GMCH DVOB or DVOC Port Unconnected
171
Miscellaneous Input Signals and Voltage Reference
171
GVREF Reference Voltage
171
AGP Port Design Guidelines
173
AGP Interface
173
Agp 2.0
173
AGP Interface Signal Groups
174
AGP Routing Guidelines
175
Timing Domain Routing Guidelines
175
Trace Length Mismatch
175
Trace Length Requirements for AGP 1X
175
Trace Spacing Requirements
175
2X/4X Timing Domain Routing Guidelines
175
Trace Length Requirements for AGP 2X/4X
175
Trace Spacing Requirements
176
Layout Guidelines for AGP 2X/4X Signals
176
Trace Length Mismatch Requirements
177
AGP Clock Skew
177
AGP Signal Noise Decoupling Guidelines
178
AGP Interface Package Lengths
178
AGP Routing Ground Reference
179
Pull-Ups
180
AGP VDDQ and VCC
181
VREF Generation for AGP 2.0 (2X and 4X)
181
AGP Compensation
181
AGP Interface (2X/4X)
181
PM_SUS_CLK/AGP_PIPE# Design Consideration
181
DPMS Circuit
182
Hub Interface
183
8-Bit Hub Interface Routing Guidelines
183
8-Bit Hub Interface Data Signals
183
Hub Interface 1.5 Data Signals Routing Summary
183
8-Bit Hub Interface Signal Referencing
184
8-Bit Hub Interface Strobe Signals
184
8-Bit Hub Interface HIREF and HI_VSWING Generation/Distribution
184
Hub Interface 1.5 Strobe Signals Routing Summary
184
GMCH Single Generated Voltage Reference Divider Circuit
187
Separate GMCH Voltage Divider Circuits for HLVREF and PSWING
188
Recommended Resistor Values for HLVREF and PSWING Divider Circuits for GMCH
188
Hub Interface Compensation
189
8-Bit Hub Interface Decoupling Guidelines
189
Terminating HI_11 if Not Used
189
Recommended Resistor Values for Single VREF/VSWING Divider Circuit
188
Intel ® 6300ESB Design Guidelines
191
Serial ATA Interface
191
Layout Guidelines
191
General Routing and Placement
191
Serial ATA Trace Separation
191
SATA BIAS Connections
192
Serial ATA Trace Length Guidelines
192
Serial ATA Trace Length Pair Matching
192
SATA Routing Summary
192
SATALED# Implementation
193
Serial ATA Trace Spacing Recommendation
192
SATA BIAS Connections
193
SATA BIAS Routing Summary
193
SATALED# Circuitry Example
193
IDE Interface
194
Cabling
194
IDE Routing Summary
194
IDE Signal Groups
194
Cable Detection for Ultra ATA/66 and Ultra ATA/100
195
Combination Host-Side/Device-Side Cable Detection
195
Device-Side Cable Detection
196
Combination Host-Side/Device-Side IDE Cable Detection
196
Device Side IDE Cable Detection
197
Primary IDE Connector Requirements
198
Connection Requirements for Primary IDE Connector
198
Secondary IDE Connector Requirements
199
Connection Requirements for Secondary IDE Connector
199
6300ESB AC'97 - Codec Connection
200
AC'97 AC_BIT_CLK Routing Summary
201
6300ESB AC'97 - AC_SDIN Topology
202
6300ESB AC'97 - AC_SDOUT/AC_SYNC Topology
202
AC'97 AC_SDOUT/AC_SYNC Routing Summary
202
AC'97 Routing
203
AC'97 AC_SDIN Routing Summary
203
Motherboard Implementation
204
Valid Codec Configurations
205
SPKR Pin Consideration
205
Supported Codec Configurations
205
AC_SDOUT Pin Consideration
206
SIU0_DTR# Pin Consideration
206
Communication Network Riser
206
AC'97 Audio Codec Detect Circuit and Configuration Options
207
CNR 1.2 AC'97 Disable and Demotion Rules for the Motherboard
207
CNR Interface
207
Signal Descriptions
207
Motherboard AC'97 CNR Implementation with a Single Codec down on Board
208
CNR Routing Summary
209
Motherboard AC'97 CNR Implementation Without Codec down on Board
209
Usb 2.0
210
Layout Guidelines
210
General Routing and Placement
210
USB 2.0 Trace Separation
211
USB BIAS Connections
211
Recommended General USB Trace Spacing (55 Ω ± 10%)
211
USB 2.0 Termination
212
USB 2.0 Trace Length Pair Matching
212
USB 2.0 Trace Length Guidelines
212
Trace Routing
211
USB 2.0 Back Panel Trace Length Guidelines
212
Plane Splits, Voids and Cut-Outs (Anti-Etch)
213
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
213
USB BIAS Connections
212
USB BIAS Routing Summary
212
USB 2.0 CNR Trace Length Guidelines
213
USB 2.0 Front Panel Trace Length Guidelines
213
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
214
USB Power Line Layout Topology
214
EMI Considerations
214
Common-Mode Chokes
215
Esd
215
Common-Mode Choke
215
Front Panel Solutions
216
Conductor Resistance (Table 6-6 from USB 2.0 Specification)
216
Internal USB Cables
216
Motherboard/Pcb Mating Connector
217
Front Panel Header Pin-Out
217
Front Panel Connector Card
218
Front Panel Header Schematic
218
Low Pin Count (LPC) Interface
219
General Routing and Placement
220
LPC Trace Length Matching
220
LPC Interface Routing Guidelines
220
LPC Interface Routing Summary
221
Smbus Architecture & Design Considerations
222
General Design Issues / Notes
222
Smbus Design Considerations
222
Smbus 2.0/Smlink Interface
221
SMBUS 2.0/Smlink Interface
222
High Power/Low Power Mixed Architecture
223
Calculating the Physical Segment Pull-Up Resistor
223
Bus Capacitance Reference Chart
224
Bus Capacitance/Pull-Up Resistor Relationship
224
Pci
224
PCI Routing Summary
224
PCI Bus Layout Example
225
PCI Bus Layout Example with IDSEL
225
PCI 33 Mhz Clock Signals Routing Summary
226
PIRQ Routing Example
227
PCI Data Signals Routing Summary
226
IOAPIC Interrupt Inputs 16 through 23 Usage
227
PCI-X Design Guidelines
228
PCI-X Frequencies
228
66 Mhz Topologies and Trace Length
229
PCI-X Routing Summary
228
PCI-X Slot/Device Configurations
228
66 Mhz PCI-X, One down Device Configuration
229
66 Mhz PCI-X, Two Slots, Two down Devices Configuration
229
66 Mhz PCI-X, Two Slots, Two down Devices Routing Length Parameters
229
66 Mhz PCI-X, One down Device Routing Length Parameters
230
66 Mhz PCI-X, Three Slot Configuration
230
66 Mhz PCI-X, Three Slot Configuration Routing Length Parameters
230
PCI-X Clock Length Matching Guidelines
231
IDSEL Series Resistor
231
66 Mhz Clock Signal Configuration
231
PCI-X Secondary Bus Reset
232
Issues with Sharing PME
232
PME# Signal Sharing
232
Secondary Bus Reset Not Utilized
232
IDSEL to PXAD Bit Assignment
232
Rtc
233
RTCX1 and SUSCLK Relationship in 6300ESB
233
RTC Crystal
234
External Circuitry for the 6300ESB RTC
234
External Capacitors
235
External Circuitry in the 6300ESB Without Use of Internal RTC
234
RTC Routing Summary
235
RTC Layout Considerations
236
RTC External Battery Connection
236
Diode Circuit to Connect RTC External Battery
237
RTC External RTCRST# Circuit
238
VBIAS DC Voltage and Noise Measurements
238
RTCRST# External Circuit for the 6300ESB RTC
238
Susclk
239
RTC-Well Input Strap Requirements
239
Serial I/O
239
Serial I/O Interface Not Utilized
239
Fwh
240
FWH Decoupling
240
FWH INIT# Voltage Compatibility
240
FWH Vendors
240
In-Circuit FWH Programming
240
FWH VPP Design Guidelines
241
GPIO Summary
242
Power Management
244
Power-Well Isolation Control Strap Requirements
244
PWRBTN# Usage Model
244
SYS_RESET# Usage Model
244
SYS_RESET# and PWRBTN# Connection
244
RTC Power Well Isolation Control
245
Miscellaneous Logic
247
Glue Chip 4
247
Discrete Logic
248
Individual Clock Breakdown
249
Clock Group Topologies and Routing Constraints
251
Host Clock Group
251
Platform Clock Routing Guidelines
249
System Clock Groups
249
Source Shunt Termination Topology
251
Host Clock Group Routing Constraints
252
Host Clock Group General Routing Guidelines
253
Clock-To-Clock Length Matching and Compensation
253
EMI Constraints
253
CLK66 Clock Group
254
CLK66 Clock Group Routing Constraints
254
CLK33 Clock Group
255
CLK66 Clock Group Topology
254
CLK33 Clock Group Routing Constraints
255
PCI Clock Group
256
CLK14 Clock Group
257
CLK33 Group Topology
255
CLK14 Clock Group Routing Constraints
257
DOTCLK Clock Group
258
CLK14 Clock Group Topology
257
DOTCLK Clock Topology
258
SSCCLK Clock Group
259
USBCLK Clock Group
260
USBCLK Clock Topology
260
SRC Clock Group
261
SRC Clock Topology
261
SCR/SCR# Routing Guidelines
261
Source Shunt Termination
261
Trace Spacing for SRC Clocks
262
SRC General Routing Guidelines
263
Schematic Checklist Summary
265
Intel ® Pentium ® M/Celeron ® M Processor Checklist
265
Connection Recommendations
265
Routing Illustration for INIT
267
In Target Probe (ITP)
268
Voltage Translation Circuit for PROCHOT
268
Decoupling Recommendations
269
VCC (Core)
269
Vcca (Pll)
269
Vccp (I/O)
269
VCC (CORE) Decoupling Recommendations
269
CK409 Clock Checklist
270
Connection Recommendations
270
Intel ® 855GME Chipset GMCH (82855GME) Checklist
272
GMCH System Memory Interface Checklist
272
System Memory
272
DDR DIMM Interface Checklist
274
Reference Voltage Level for SMVREF
274
DIMM Decoupling Recommendation Checklist
275
Frontside Bus (FSB) Checklist
275
FSB Checklist
275
Hub Interface Checklist
277
Voltage Generation Circuit
277
Digital Video out (DVO) Checklist
278
Graphics Interfaces Checklist
278
Low Voltage Digital Signalling (LVDS) Checklist
278
DVO Checklist
278
Digital-To-Analog Converter (DAC) Checklist
280
LVDS Checklist
278
DAC Checklist
280
Miscellaneous Signal Checklist
281
GMCH Decoupling Recommendations Checklist
281
Intel ® Pentium ® M/Celeron ® M Processor GST[2:0] Configurations
281
GST[2:0] Configurations
281
GMCH Decoupling Recommendations Checklist
282
Intel ® 6300ESB Checklist
283
PCI-X Interface Checklist
283
PCI Interface Checklist
285
FWH/LPC Interface Checklist
288
Hub Interface Checklist
288
GPIO Checklist
289
Power Management Checklist
290
USB Checklist
290
CPU Signals Checklist
291
RTC Checklist
292
System Management Checklist
292
UART Checklist
293
AC'97 Checklist
294
Miscellaneous Signals
294
Miscellaneous Signals Checklist
294
Serial ATA Checklist
295
IDE Checklist
295
Power Checklist
297
Layout Checklist
299
Processor Checklist
299
Intel ® 855GME Chipset GMCH (82855GME) Layout Checklist
307
Intel ® 855GME Chipset GMCH Layout Checklist
308
Intel ® 6300ESB Layout Checklist
312
8-Bit Hub Interface Layout Checklist
312
Serial ATA Interface Layout Checklist
313
IDE Interface Layout Checklist
314
USB 2.0 Layout Checklist
314
AC'97 Layout Checklist
315
RTC Layout Checklist
315
FWH Decoupling Layout Checklist
316
PCI Layout Checklist
316
PCI-X Layout Checklist
316
Power Delivery Checklist
317
4
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Intel 855GME Specifications
General
Brand
Intel
Model
855GME
Category
Computer Hardware
Language
English
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