11-14 Limit Testing Models 2500 and 2502 User’s Manual
Multiple-element device binning
Figure 11-8 shows a basic binning system to test multiple DUTs. Note that this system
requires a scanner card that is installed in a switching mainframe. Scanner card switching
is controlled through the Trigger Link. End binning control is required for this test system;
therefore, the grading mode must be used.
Trigger operations for the scanner and Model 2500 must be configured appropriately for
this test. In general, the scanner must be configured to scan three channels, and the Model
2500 must be configured to perform a 3-point sweep and output a trigger to the scanner
after each measurement. See Section 10 for details.
When the testing process is started, Ch. 1 of the scanner card closes, and DUT 1 is mea-
sured. Two events occur concurrently after the measurement is completed: DUT 2 is
tested, and the Model 2500 sends a trigger pulse to the switching mainframe causing Ch. 1
to open and Ch. 2 to close. Assuming there is no failure, a measurement is then performed
on DUT 2. While DUT 2 is being tested, Ch. 2 opens and Ch. 3 closes. Again assuming no
failure, a measurement is performed on DUT 3 and it is then tested. Assuming that all the
tests pass on all DUTs, the device package is placed in the pass bin.
If any of the DUTs fails a test, the FAIL message is displayed, and the digital output infor-
mation for the first failure is stored in memory (assuming that END binning control is
selected). After the sweep is completed, the Model 2500 sends the output pattern stored in
memory. This is the output pattern for the first test failure. The component handler places
the DUT package into the bin assigned to that particular failure.
The handler selects the next DUT, and the testing process is repeated.
Digital output clear pattern
After every binning operation, the digital output needs to be reset to a clear pattern, which
serves as a no action condition for the component handler.
The Model 2500 can be programmed to automatically clear the digital output after the
pass or fail pattern is sent. With auto-clear, you must specify the required pulse width
(delay) for the pass or fail pattern. When not using auto-clear, you must return the digital
output to its clear pattern from the DIGOUT AUTO-CLEAR option of the CONFIG
LIMIT menu. This option also sets the pass/fail pattern and pulse width.
Enabling auto-clear
To enable auto-clear:
1. Press CONFIG then LIMIT.
2. Select DIGOUT, then press ENTER.
3. Choose AUTO-CLEAR, then press ENTER.
4. Select ENABLE, then press ENTER.
5. At the prompts, set the auto-clear pulse width (0s to 60s) and clear bit pattern (0 to 15,
4-bit; 0 to 7, 3-bit size). Use EXIT to return to normal display.
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