14-14 Status Structure Models 2500 and 2502 User’s Manual
Measurement event register
The used bits of the measurement event register (Figure 14-6) are described as follows:
• Bit B0, Limit 1 Summary (L1) — Set bit indicates Limit 1 summary information is
available in the :FORM:ELEM STAT element (see Section 17, “FORMat subsystem”).
• Bit B1, Limit 2 Summary (L2) — Set bit indicates Limit 2 summary information is
available in the :FORM:ELEM STAT element.
• Bit B2, Limit 3 Summary (L3) — Set bit indicates Limit 3 summary information is
available in the :FORM:ELEM STAT element.
• Bit B3, Limit 4 Summary (L4) — Set bit indicates Limit 4 summary information is
available in the :FORM:ELEM STAT element.
• Bit B4, Limit Fail High (LFH) — Set bit indicates that one of the high limit tests has
failed.
• Bit B5, Limits Pass (LP) — Set bit indicates that all limit tests passed.
• Bit B6, Reading Available (RAV) — Set bit indicates that a reading was taken and
processed.
• Bit B7, Reading Overflow (ROF) — Set bit indicates that the current reading exceeds
the selected measurement range of the Model 2500.
• Bit B8, Buffer Available (BAV) — Set bit indicates that there are at least two readings
in the buffer.
• Bit B9, Buffer Full (BFL) — Set bit indicates that the trace buffer is full.
• Bit B10 — Not used.
• Bit B11, Output Enable Asserted (OE) — Set bit indicates that the Digital I/O port
output enable line is at digital low (asserted). Source outputs can be turned on.
• Bit B12 — Not used.
• Bit B13, Source 1 Compliance (S1C) — Set bit indicates that the channel 1 voltage
source is in compliance.
• Bit B14, Source 2 Compliance (S2C) — Set bit indicates that the channel 2 voltage
source is in compliance.
• Bit B15 — Not used.
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