NXP Semiconductors MPC5777C - Page 103

3.5.4.1.6 Rx FIFOs
Rx FIFO 0 and Rx FIFO 1 can be configured to hold up to 64 elements each.
Configuration of the two Rx FIFOs is done via registers RXF0C and RXF1C.
Received messages that passed acceptance filtering are transferred to the Rx FIFO as
configured by the matching filter element. For a description of the filter mechanisms
available for Rx FIFO 0 and Rx FIFO 1 see Acceptance filtering. The Rx FIFO element
is described in Rx Buffer and FIFO Element.
To avoid an Rx FIFO overflow, the Rx FIFO watermark can be used. When the Rx FIFO
fill level reaches the Rx FIFO watermark configured by RXFnC[FnWM], interrupt flag
IR[RFnW] is set. When the Rx FIFO Put Index reaches the Rx FIFO Get Index an Rx
FIFO Full condition is signalled by RXFnS[FnF]. In addition interrupt flag IR[RFnF] is
set.

Figure 3-55. Rx FIFO Status
When reading from an Rx FIFO, Rx FIFO Get Index RXFnS[FnGI] x FIFO Element Size
has to be added to the corresponding Rx FIFO start address RXFnC[FnSA].
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 103