Table 3-59. Rx Buffer / FIFO Element Size
RXESC.RBDS[2:0] RXESC.FnDS[2:0] Data Field [bytes] FIFO Element Size [RAM words]
000 8 4
001 12 5
010 16 6
011 20 7
100 24 8
101 32 10
110 48 14
111 64 18
3.5.4.1.6.1 Rx FIFO Blocking Mode
The Rx FIFO blocking mode is configured by RXFnC[FnOM] = 0. This is the default
operation mode for the Rx FIFOs.
When an Rx FIFO full condition is reached (RXFnS[FnPI] = RXFnS[FnGI]), no further
messages are written to the corresponding Rx FIFO until at least one message has been
read out and the Rx FIFO Get Index has been incremented. An Rx FIFO full condition is
signalled by RXFnS[FnF] = 1. In addition interrupt flag IR[RFnF] is set.
In case a message is received while the corresponding Rx FIFO is full, this message is
discarded and the message lost condition is signalled by RXFnS[RFnL] = 1. In addition
interrupt flag IR[RFnL] is set.
3.5.4.1.6.2 Rx FIFO Overwrite Mode
The Rx FIFO overwrite mode is configured by RXFnC[FnOM] = 1.
When an Rx FIFO full condition (RXFnS[FnPI] = RXFnS[FnGI]) is signalled by
RXFnS[FnF] = 1, the next message accepted for the FIFO will overwrite the oldest FIFO
message. Put and get index are both incremented by one.
When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is
signalled, reading of the Rx FIFO elements should start at least at get index + 1. The
reason for that is, that it might happen, that a received message is written to the Message
RAM (put index) while the CPU is reading from the Message RAM (get index). In this
case inconsistent data may be read from the respective Rx FIFO element. Adding an
offset to the get index when reading from the Rx FIFO avoids this problem. The offset
depends on how fast the CPU accesses the Rx FIFO. The following figure shows an
offset of two with respect to the get index when reading the Rx FIFO. In this case the two
messages stored in element 1 and 2 are lost.
Functional Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
104 Freescale Semiconductor, Inc.
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