After the last word of a matching received message has been written to the Message
RAM, the respective New Data flag in register NDAT1,2 is set. As long as the New Data
flag is set, the respective Rx Buffer is locked against updates from received matching
frames. The New Data flags have to be reset by the Host by writing a 1 to the respective
bit position.
While an Rx Buffer’s New Data flag is set, a Message ID Filter Element referencing this
specific Rx Buffer will not match, causing the acceptance filtering to continue. Following
Message ID Filter Elements may cause the received message to be stored into another Rx
Buffer, or into an Rx FIFO, or the message may be rejected, depending on filter
configuration
3.5.4.1.7.1 Rx Buffer Handling
• Reset interrupt flag IR[DRX]
• Read New Data registers
• Read messages from Message RAM
• Reset New Data flags of processed messages
3.5.4.1.8 Debug on CAN Support
Debug messages are stored into Rx Buffers. For debug handling three consecutive Rx
buffers (e.g. #61, #62, #63) have to be used for storage of debug messages A, B, and C.
The format is the same as for an Rx Buffer or an Rx FIFO element.
Advantage: Fixed start address for the DMA transfers (relative to RXBC[RBSA]), no
additional configuration required.
For filtering of debug messages Standard / Extended Filter Elements with SFEC / EFEC
= 111 have to be set up. Messages matching these filter elements are stored into the Rx
Buffers addressed by SFID2 / EFID2[5:0].
After message C has been stored, the DMA request output m_can_dma_req is activated
and the three messages can be read from the Message RAM under DMA control. The
RAM words holding the debug messages will not be changed by the M_CAN while
m_can_dma_req is activated. The behaviour is similar to that of an Rx Buffers with its
New Data flag set.
After the DMA has completed the DMA unit sets m_can_dma_ack. This resets
m_can_dma_req. Now the M_CAN is prepared to receive the next set of debug
messages.
NOTE
To use full ‘Debug on CAN Support’ feature on a M_CAN
instance, a DMA channel is required. Refer to device DMA
Functional Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
106 Freescale Semiconductor, Inc.
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