NXP Semiconductors MPC5777C Reference Manual

PCM_IAHB_BE1 field descriptions (continued)
Field Description
5
PRE_CORE1_D
Pending Read Enable Core1 Data
This bit controls the bus gasket’s handling of pending read transactions.
0 Pending reads are disabled.
1 Pending reads are enabled.
6
BRE_CORE1_D
Burst Read Enable Core1 Data
This bit controls the bus gasket’s handling of burst read transactions.
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
7
BWE_CORE1_D
Burst Write Enable Core1 Data
This bit controls the bus gasket’s handling of burst write transactions.
0 Burst writes are converted into a series of single transactions on the slave side of the gasket.
1 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise”
such that an error response on any beat of the burst is reported on the last beat.
8–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
PRE_CORE1_I
Pending Read Enable Core1 Instruction
This bit controls the bus gasket’s handling of pending read transactions.
0 Pending reads are disabled.
1 Pending reads are enabled.
14
BRE_CORE1_I
Burst Read Enable Core1 Instruction
This bit controls the bus gasket’s handling of burst read transactions.
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
15
BWE_CORE1_I
Burst Write Enable Core1 Instruction
This bit controls the bus gasket’s handling of burst write transactions.
0 Burst writes are converted into a series of single transactions on the slave side of the gasket.
1 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise”
such that an error response on any beat of the burst is reported on the last beat.
16–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21
PRE_CORE0_D
Pending Read Enable Core0 Data
This bit controls the bus gasket’s handling of pending read transactions.
0 Pending reads are disabled
1 Pending reads are enabled.
22
BRE_CORE0_D
Burst Read Enable Core0 Data
This bit controls the bus gasket’s handling of burst read transactions.
Table continues on the next page...
PCM memory map and register descriptions
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
14 Freescale Semiconductor, Inc.

NXP Semiconductors MPC5777C Specifications

General

Brand	NXP Semiconductors
Model	MPC5777C
Category	Motherboard
Language	English