NXP Semiconductors MPC5777C - Page 17

PCM_IAHB_BE2 field descriptions (continued)
Field Description
0 Pending reads are disabled.
1 Pending reads are enabled.
14
BRE_M6
Burst Read Enable Master Port 6 Concentrator
This bit controls the bus gasket’s handling of burst read transactions.
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
15
BWE_M6
Burst Write Enable Master Port 6 Concentrator
This bit controls the bus gasket’s handling of burst write transactions.
0 Burst writes are converted into a series of single transactions on the slave side of the gasket.
1 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise”
such that an error response on any beat of the burst is reported on the last beat.
16–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21
PRE_DMA_B
Pending Read Enable eDMA_B
This bit controls the bus gasket’s handling of pending read transactions.
0 Pending reads are disabled
1 Pending reads are enabled.
22
BRE_DMA_B
Burst Read Enable eDMA_B
This bit controls the bus gasket’s handling of burst read transactions.
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
23
BWE_DMA_B
Burst Write Enable eDMA_B
This bit controls the bus gasket’s handling of burst write transactions.
0 Burst writes are converted into a series of single transactions on the slave side of the gasket.
1 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise”
such that an error response on any beat of the burst is reported on the last beat.
24–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
PRE_DMA_A
Pending Read Enable eDMA_A
This bit controls the bus gasket’s handling of pending read transactions.
0 Pending reads are disabled.
1 Pending reads are enabled.
30
BRE_DMA_A
Burst Read Enable eDMA_A
This bit controls the bus gasket’s handling of burst read transactions.
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
Table continues on the next page...
Chapter 2 Platform Configuration Module (PCM)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 17