NXP Semiconductors MPC5777C - Power Supply Configuration on Motherboard

Section number Title Page
3.2.4 Dual Interrupt Lines.............................................................................................................................................26
3.3 Memory Map and Register Description............................................................................................................................27
3.3.1 Core Release Register (M_CAN_CREL)............................................................................................................28
3.3.2 Endian Register (M_CAN_ENDN).....................................................................................................................29
3.3.3 Fast Bit Timing and Prescaler Register (M_CAN_FBTP)..................................................................................30
3.3.4 Test Register (M_CAN_TEST)...........................................................................................................................32
3.3.5 RAM Watchdog Register (M_CAN_RWD)........................................................................................................33
3.3.6 CC Control Register (M_CAN_CCCR)..............................................................................................................34
3.3.7 Bit Timing and Prescaler Register (M_CAN_BTP)............................................................................................36
3.3.8 Timestamp Counter Configuration Register (M_CAN_TSCC)..........................................................................38
3.3.9 Timestamp Counter Value Register (M_CAN_TSCV).......................................................................................38
3.3.10 Timeout Counter Configuration Register (M_CAN_TOCC)..............................................................................39
3.3.11 Timeout Counter Value Register (M_CAN_TOCV)...........................................................................................40
3.3.12 Error Counter Register (M_CAN_ECR)..............................................................................................................41
3.3.13 Protocol Status Register (M_CAN_PSR)............................................................................................................42
3.3.14 Interrupt Register (M_CAN_IR)..........................................................................................................................45
3.3.15 Interrupt Enable Register (M_CAN_IE)..............................................................................................................49
3.3.16 Interrupt Line Select Register (M_CAN_ILS).....................................................................................................52
3.3.17 Interrupt Line Enable Register (M_CAN_ILE)...................................................................................................55
3.3.18 Global Filter Configuration Register (M_CAN_GFC)........................................................................................56
3.3.19 Standard ID Filter Configuration Register (M_CAN_SIDFC)............................................................................57
3.3.20 Extended ID Filter Configuration Register (M_CAN_XIDFC)..........................................................................58
3.3.21 Extended ID and Mask Register (M_CAN_XIDAM).........................................................................................59
3.3.22 High Priority Message Status Register (M_CAN_HPMS)..................................................................................59
3.3.23 New Data 1 Register (M_CAN_NDAT1)...........................................................................................................60
3.3.24 New Data 2 Register (M_CAN_NDAT2)...........................................................................................................61
3.3.25 Rx FIFO 0 Configuration Register (M_CAN_RXF0C)......................................................................................61
3.3.26 Rx FIFO 0 Status Register (M_CAN_RXF0S)....................................................................................................62
3.3.27 Rx FIFO 0 Acknowledge Register (M_CAN_RXF0A)......................................................................................63
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
4 Freescale Semiconductor, Inc.