Section number Title Page
3.3.28 Rx Buffer Configuration Register (M_CAN_RXBC).........................................................................................64
3.3.29 Rx FIFO 1 Configuration Register (M_CAN_RXF1C)......................................................................................64
3.3.30 Rx FIFO 1 Status Register (M_CAN_RXF1S)....................................................................................................65
3.3.31 Rx FIFO 1 Acknowledge Register (M_CAN_RXF1A)......................................................................................66
3.3.32 Rx Buffer / FIFO Element Size Configuration Register (M_CAN_RXESC).....................................................67
3.3.33 Tx Buffer Configuration Register (M_CAN_TXBC)..........................................................................................69
3.3.34 Tx FIFO/Queue Status Register (M_CAN_TXFQS)...........................................................................................70
3.3.35 Tx Buffer Element Size Configuration (M_CAN_TXESC)................................................................................71
3.3.36 Tx Buffer Request Pending Register (M_CAN_TXBRP)...................................................................................72
3.3.37 Tx Buffer Add Request Register (M_CAN_TXBAR)........................................................................................73
3.3.38 Tx Buffer Cancellation Request Register (M_CAN_TXBCR)...........................................................................73
3.3.39 Tx Buffer Transmission Occurred Register (M_CAN_TXBTO)........................................................................74
3.3.40 Tx Buffer Cancellation Finished Register (M_CAN_TXBCF)...........................................................................74
3.3.41 Tx Buffer Transmission Interrupt Enable Register (M_CAN_TXBTIE)............................................................75
3.3.42 Tx Buffer Cancellation Finished Interrupt Enable Register (M_CAN_TXBCIE)..............................................75
3.3.43 Tx Event FIFO Configuration Register (M_CAN_TXEFC)...............................................................................76
3.3.44 Tx Event FIFO Status Register (M_CAN_TXEFS)............................................................................................77
3.3.45 Tx Event FIFO Acknowledge Register (M_CAN_TXEFA)...............................................................................78
3.4 Message RAM..................................................................................................................................................................78
3.4.1 Rx Buffer and FIFO Element...............................................................................................................................79
3.4.2 Tx Buffer Element...............................................................................................................................................81
3.4.3 Tx Event FIFO Element.......................................................................................................................................83
3.4.4 Standard Message ID Filter Element...................................................................................................................84
3.4.5 Extended Message ID Filter Element..................................................................................................................85
3.5 Functional Description......................................................................................................................................................87
3.5.1 Operating Modes..................................................................................................................................................87
3.5.2 Timestamp Generation.........................................................................................................................................96
3.5.3 Timeout Counter..................................................................................................................................................97
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 5