Omron SYSMAC CJ - REFERENCE MANUAL 08-2008 - Page 1324

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CS-series Instruction Execution Times and Number of Steps Section 4-1
4-1-1 Sequence Input Instructions
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Instruction Mnemonic Code Length
(steps)
ON execution time (µs) Conditions
CPU6@HCPU4@HCPU6@ CPU4@
LOAD LD --- 1 0.02 0.04 0.04 0.08 ---
!LD --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
LOAD NOT LD NOT --- 1 0.02 0.04 0.04 008 ---
!LD NOT --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
AND AND --- 1 0.02 0.04 0.04 0.08 ---
!AND --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
AND NOT AND NOT --- 1 0.02 0.04 0.04 0.08 ---
!AND NOT --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
OR OR --- 1 0.02 0.04 0.04 0.08 ---
!OR --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
OR NOT OR NOT --- 1 0.02 0.04 0.04 0.08 ---
!OR NOT --- 2 +21.14 +21.16 +21.16 +21.16 Increase for CS
Series
+45.1 +45.1 +45.1 +45.1 Increase for
C200H
AND LOAD AND LD --- 1 0.02 0.04 0.04 0.08 ---
OR LOAD OR LD --- 1 0.02 0.04 0.04 0.08 ---
NOT NOT 520 1 0.02 0.04 0.04 0.08 ---
CONDITION
ON
UP 521 3 0.3 0.42 0.46 0.54 ---
CONDITION
OFF
DOWN 522 4 0.3 0.42 0.46 0.54 ---
LOAD BIT
TEST
LD TST 350 4 0.14 0.24 0.25 0.37 ---
LOAD BIT
TEST NOT
LD TSTN 351 4 0.14 0.24 0.25 0.37 ---
AND BIT
TEST NOT
AND TSTN 351 4 0.14 0.24 0.25 0.37 ---
OR BIT TEST OR TST 350 4 0.14 0.24 0.25 0.37 ---
OR BIT TEST
NOT
OR TSTN 351 4 0.14 0.24 0.25 0.37 ---