1309
CS-series Instruction Execution Times and Number of Steps Section 4-1
CONDI-
TIONAL
BLOCK
EXIT
EXIT (bit
address)
806 2 6.8 13.5 16.3 16.3 EXIT condition
satisfied
4.7 7.2 10.7 10.7 EXIT condition
not satisfied
CONDI-
TIONAL
BLOCK
EXIT (NOT)
EXIT NOT
(bit address)
806 2 12.4 14.0 16.8 16.8 EXIT condition
satisfied
7.1 7.6 11.2 11.2 EXIT condition
not satisfied
Branching IF (execution
condition)
802 1 4.6 4.8 7.2 7.2 IF true
6.7 7.3 10.9 10.9 IF false
Branching IF (relay
number)
802 2 6.8 7.2 10.4 10.4 IF true
9.0 9.6 14.2 14.2 IF false
Branching
(NOT)
IF NOT
(relay num-
ber)
802 2 7.1 7.6 10.9 10.9 IF true
9.2 10.1 14.7 14.7 IF false
Branching ELSE 803 1 6.2 6.7 9.9 9.9 IF true
6.8 7.7 11.2 11.2 IF false
Branching IEND 804 1 6.9 7.7 11.0 11.0 IF true
4.4 4.6 7.0 7.0 IF false
ONE
CYCLE AND
WAIT
WAIT (exe-
cution condi-
tion)
805 1 12.6 13.7 16.7 16.7 WAIT condition
satisfied
3.9 4.1 6.3 6.3 WAIT condition
not satisfied
ONE
CYCLE AND
WAIT
WAIT (relay
number)
805 2 12.0 13.4 16.5 16.5 WAIT condition
satisfied
6.1 6.5 9.6 9.6 WAIT condition
not satisfied
ONE
CYCLE AND
WAIT (NOT)
WAIT NOT
(relay num-
ber)
805 2 12.2 13.8 17.0 17.0 WAIT condition
satisfied
6.4 6.9 10.1 10.1 WAIT condition
not satisfied
COUNTER
WAIT
CNTW 814 4 17.9 22.6 27.4 27.4 Default setting
19.1 23.9 28.7 28.7 Normal execu-
tion
CNTWX 818 4 17.9 22.6 --- --- Default setting
19.1 23.9 --- --- Normal execu-
tion
TEN-MS
TIMER
WAIT
TMHW 815 3 25.8 27.9 34.1 34.1 Default setting
20.6 22.7 28.9 28.9 Normal execu-
tion
TMHWX 817 3 25.8 27.9 --- --- Default setting
20.6 22.7 --- --- Normal execu-
tion
9.3 10.8 --- --- LEND condition
not satisfied
Loop Control LOOP 809 1 7.9 9.1 12.3 12.3 ---
Loop Control LEND (exe-
cution condi-
tion)
810 1 7.7 8.4 10.9 10.9 LEND condition
satisfied
6.8 8.0 9.8 9.8 LEND condition
not satisfied
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (µs) Conditions
CPU-6@HCPU-4@HCPU-6@ CPU-4@
To Next Page
Loading...
