R&S®SML / R&S®SMV03 Status Reporting System
1090.3123.12 E-6 5.19
Description of Status Registers
Status Byte (STB) and Service Request Enable Register (SRE)
The STB is already defined in IEEE 488.2. It provides a rough overview of the instrument status by
collecting the pieces of information of the lower registers. It can thus be compared with the CONDition
part of an SCPI register and assumes the highest level within the SCPI hierarchy. A special feature is
that bit 6 acts as the sum bit of the remaining bits of the status byte.
The status byte is read using the command *STB? or a serial poll.
The STB is assigned an SRE. The SRE functionally corresponds to the ENABle part of the SCPI
registers. Each bit of the STB is assigned a bit of the SRE. Bit 6 of the SRE is ignored. If a bit is set in
the SRE and the associated bit in the STB changes from 0 to 1, a service request (SRQ) is generated
on the IEC/IEEE bus which triggers an interrupt in the controller (if the controller is configured
correspondingly) and can be further processed there.
The SRE can be set using the command *SRE and read using the command *SRE?.
Table 5-2 Meaning of the bits used in the status byte
Bit No. Meaning
2
Error Queue Not Empty
This bit is set if an entry is made in the error queue.
If the bit is enabled by the SRE, each entry in the error queue generates a service request. Thus an error can be
recognized and determined in greater detail by polling the error queue. The poll provides an informative error
message. This procedure is recommended since it considerably reduces the problems involved in IEC/IEEE-bus
control.
3
QUEStionable Status sum bit
This bit is set if an EVENt bit is set in the QUEStionable status register and the associated ENABle bit is set to 1.
If the bit is set, this indicates a questionable instrument status which can be determined in greater detail by
polling the QUEStionable status register.
4
MAV bit (M
essage AVailable)
This bit is set if a message is available in the output buffer which can be read.
The bit can be used for the automatic reading of data from the instrument to the controller (see chapter 7,
"Programming Examples").
5
ESB bit
Sum bit of event status register. It is set if one of the bits of the event status register is set and enabled in the
event status enable register.
If the bit is set, this indicates a serious error which can be determined in greater detail by polling the event status
register.
6
MSS bit (M
aster Status Summary bit)
This bit is set if the instrument triggers a service request. This is the case if one of the other bits of this register
is set together with its mask bit in the service request enable (SRE) register.
7
OPERation Status Register sum bit
This bit is set if an EVENt bit is set in the OPERation status register and the associated ENABle bit is set to 1.
If the bit is set, this indicates that the instrument is just carrying out an action. The type of action can be
determined by polling the OPERation status register.
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