Toshiba TECRA 9100 Series - Page 24

1 Hardware Overview 1.2 System Unit Block Diagram
1-10 TECRA 9100 Maintenance Manual (960-347)
 Brookdale-M Graphics and Memory Controller Hub (MCH3-M)
• One Intel 82845MP is used.
• Features:
– Processor/Host Bus Support
– Integrated SDRAM Controller
– Accelerated Graphics Port (AGP R2.0) Interface Multiplexed with
Internal Graphics
– Hub Link Interface
 I/O Controller Hub 3 (ICH3-M)
• One Intel 82801LAM is used.
• This gate array has the following features:
− Enhanced DMA featuring Mobile PC/PCI
− Serial Interrupt Controller
− Interrupt Controller
− Power Management Logic
− Suspend/Resume Logic
− Low Pin count (LPC) Bus Controller (EC/KBC, Super I/O)
− Firmware Hub (FWH) I/F supports BIOS
− BusMasterIDE/UltraDMA100/66/33
− Real-Time Clock
− Stop Clock
− PCI Clock stop
− ACPI
− AC'97 I/F
− USB Controller (UHCI)
 PC Card Controller Gate Array
• One YEBISU3S gate array is used.
• This gate array has the following functions and components.
− PCI interface (PCI Revision2.2)
− Chipset interface
Intel serial interrupt
− CardBus/PC Card controller (Yenta Version2.2)
Parallel power supply control (Toshiba style) and serial power supply
control (Texas Instruments style)
− SD memory card controller (SDHC Ver.01)
− SDIO card controller (Ver.1.0)
− Smart Card interface
− SIO controller