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12.1.11 Functions and explanations
Software gate and hardware gate
A release signal is required in order to start counting/measuring.
The counter module controls the starting and stopping of the counting/measuring operation by
means of so-called ”gates”. A software gate and a hardware gate are provided for implementing this
control both via the software (process output/control interface) and via a physical output:
The software gate initiates the release via the SW_GATE control bit. The release is activated by the
rising edge from 0 1 of the SW_GATE control bit. If Function DI = HW Gate is set at the same
time, it should be ensured that a High signal is present at the digital input. With DI digital input =
normal this is 24 VDC.
A stop is initiated by resetting the SW_GATE control bit from 1 0. If Function DI = HW Gate is
set, the counting/measuring operation can be stopped either by the software gate or the hard-
ware gate.
A Hardware gate initiates a release via a 24 VDC signal at the digital input. This function is config-
ured with Function DI = HW gate. The release is then only possible if the SW_GATE bit =1 at the
same time.
This bit is set when there is a rising edge from 0 1 at the input and reset with a falling edge from
0.
The edge change can be reversed by inverting the digital input.
Invert digital input = yes
Synchronization
Synchronization must be configured before operating the counter module (Function DI = Synchro-
nization when edge positive). The rising edge of a reference signal at the input is used to set the
counter to the load value.
A single-action or periodical synchronization can be selected. This is possible under the following
conditions:
The counting operation must be started with the software release.
The Release Synchronization (CRTL_SYN) control bit must be set.
With single-action synchronization the first 0 1 edge at the digital input sets the counter to the
load value after the release bit is set.
With periodical synchronization the first and every subsequent 1 edge at the digital input sets
the counter to the load value after the release bit is set.
After synchronization is successfully completed the STS_SYN status bit is set. It can only reset by
the RES_STS control bit.
The STS_DI check-back bit indicates the status of the reference signal at the digital input.
When single-action synchronization is set, a subsequent synchronization operation can be initiated
by resetting and setting the Release synchronization (CRTL_SYN) control bit. This is executed on the
next 0 1 edge at the digital input.
NOTE
If the counting operation is aborted, counting begins from the load value on restart. If the
counting operation is aborted, counting begins from the load value on restart. If the
counting operation is interrupted, however, the counter continues on restart from the
actual counter value.
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