6253 DC Voltage Current Source/Monitor Operation Manual
5.6 Status Register Structure
5-17
Common conditions in which the Status Byte Register is cleared
• All cleared when the power is turned ON.
• All cleared by *CLS except that MAV is not cleared if data exists in the output buffer.
• Not cleared even if read by *STB?
Conditions in which the Service Request Enable Register is cleared
• Cleared when the power is turned ON.
• Cleared when the *SRE0 command is executed.
Table 5-5 Status Byte Register (STB)
bit Name Description
0 Not in use Always set to 0.
1 Not in use Always set to 0.
2 Not in use Always set to 0.
3DSB
Device Event Status
ON : Set to 1 when any of the DESR incidents occurs and the bit is set to 1, if the
corresponding DESER bit is also 1.
OFF : Set to 0 when DESR is cleared by reading (DSR? ).
4MAV
Message Available
ON : Set to 1 when output data is entered in the output buffer.
OFF : Set to 0 when the output buffer is read and becomes empty.
5ESB
Standard Event Status
ON : Set to 1 when any of the SESR incidents occurs and the bit is set to 1, if the
corresponding SESER bit is also 1.
OFF: Set to 0 when SESR is cleared by reading (*ESR? ).
6MSS
Master Summary
ON : Set to 1 when any of the STB incidents occurs and the bit is set to 1, if the
corresponding SRER bit is also 1.
RQS
Request Service
ON : Set to 1 when MSS is set to 1 and SRQ is generated.
OFF : Set to 0 when STB is read by a serial poll.
7 Not in use Always set to 0.
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