5 Serial Ports
5 – 2
A SPORT receives serial data on its DR input and transmits serial data on
its DT output. It can receive and transmit simultaneously, for full duplex
operation. The data bits are synchronous to the serial clock SCLK, which is
an output if the processor generates this clock or an input if the clock is
generated externally. Frame synchronization signals RFS and TFS are used
to indicate the start of a serial data word or stream of serial words.
Figure 5.1, shows a simplified block diagram of a single SPORT. Data to
be transmitted is written from an internal processor register to the
SPORT’s TX register via the DMD bus. This data is optionally compressed
in hardware, then automatically transferred to the transmit shift register.
The bits in the shift register are shifted out on the SPORT’s DT pin, MSB
first, synchronous to the serial clock. The receive portion of the SPORT
accepts data from the DR pin, synchronous to the serial clock. When an
entire word is received, the data is optionally expanded, then
automatically transferred to the SPORT’s RX register, where it is available
to the processor.
The following is a list of SPORT characteristics. Many of the SPORT
characteristics are configurable to allow flexibility in serial
communication.
Companding
Hardware
Receive Shift Register
16
16
TXn
Transmit Data Register
Transmit Shift Register
16
16
DMD Bus
16
DT DR
Serial
Control
SCLKTFS RFS
Internal
Serial
Clock
Generator
RXn
Receive Data Register
Figure 5.1 Serial Port Block Diagram
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