5 Serial Ports
5 – 16
(continued from previous page)
{SPORT0 inits}
{Assumes a CLKIN of 12.288 MHz. Internally generated}
{SCLK will be 2.048 MHz, and framing sync of 8 kHz}
AX0 = 255;
DM(0x3FF4) = AX0; {RFSDIV = 256, 256 SCLKs between}
{frame syncs: 8 kHz framing}
AX0 = 2;
DM(0x3FF5) = AX0; {SCLK = 2.048 MHz}
AX0 = 0x6B27;
DM(0x3FF6) = AX0; {internal SCLK, RFS and TFS}
{normal framing, mu-law companding}
{8 bit words}
{SPORT ENABLE}
IFC = 0x1E; {clear any extraneous SPORT
interrupts}
ICNTL = 0; {interrupt nesting disabled}
AX0 = 0x1C1F; {both SPORTs enabled, BWAIT and}
DM(0x3FFF) = AX0; {PWAIT left as default}
IMASK = 0x1E; {SPORT interrupts are enabled}
{—— END SPORT INITIALIZATIONS ——}
Figure 5.9 Example SPORT Configuration Code
5.9 TIMING
EXAMPLES
This section contains examples of some combinations of the various
framing options. The timing diagrams show relationships between
signals, but are not scaled to show the actual timing parameters of the
processor. Consult the data sheet for actual timing parameters and values.
The examples assume a word length of four bits, that is, SLEN = 3.
Framing signals are active high, that is, INVRFS = 0 and INVTFS = 0.
The value of the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2
for SPORT1) is shown for each example. In these binary values, 1= high, 0
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