System Interface9
9 – 28
Pin Direction State During Powerdown
SCLK1 I Active
SCLK1 O Driven to a static level if internal, high impedance otherwise
TFS1/
IRQ1 I Active if SPORT 1 is enabled or configured alternate (IRQ1)
TFS1 O Driven if SPORT 1 is enabled and configured for internal transmit framing,
high impedance otherwise
RFS1/
IRQ0 I Active if SPORT 1 is enabled or configured alternate (IRQ0)
RFS1 O Driven if SPORT 1 is enabled and configured for internal receive framing,
high impedance otherwise
DR1/FLAGIN I Active if SPORT 1 is enabled or configured alternate (FLAGIN)
DT1/FLAGOUT O Driven if serial port operating. Output may be static or changing depending
upon serial clock. Driven if SPORT 1 is enabled or configured alternate
(FLAGOUT)
FL<2:0> O Driven to previous value
PF<7:0> I/O (ADSP-2181) Active
BMODE I Active
IRD I(ADSP-2181) Active, if IS asserted
IWR I(ADSP-2181) Active, if IS asserted
IS I(ADSP-2181) Active
IAL I (ADSP-2181) Active, if
IS asserted
IAD I/O (ADSP-2181) Active, if an operation in progress
IACK O(ADSP-2181) Active
HSIZE I (ADSP-2171, ADSP-21msp5x) Active
HMD0 I (ADSP-2171, ADSP-21msp5x) Active
HMD1 I (ADSP-2171, ADSP-21msp5x) Active
HSEL I (ADSP-2171, ADSP-21msp5x) Active
HRD I (ADSP-2171, ADSP-21msp5x) Active
HWR I (ADSP-2171, ADSP-21msp5x) Active
HADR<2:0> I (ADSP-2171, ADSP-21msp5x) Active
HDATA<15:0> I (ADSP-2171, ADSP-21msp5x) Active if host writing or HMD1 and
HA2/HALE HIGH, inactive otherwise
HDATA<15:0> O (ADSP-2171, ADSP-21msp5x) Driven if host reading, high impedance otherwise
HACK O (ADSP-2171, ADSP-21msp5x) Driven
VIN (NORM) I (ADSP-21msp5x) Inactive, set analog powerdown bit
VIN (AUX) I (ADSP-21msp5x) Inactive, set analog powerdown bit
VFB (NORM) O (ADSP-21msp5x) Inactive, set analog powerdown bit
VFB (AUX) O (ADSP-21msp5x) Inactive, set analog powerdown bit
VOUTP O (ADSP-21msp5x) Driven low in powerdown
VOUTN O (ADSP-21msp5x) Driven low in powerdown
VREF O (ADSP-21msp5x) Reference turned off
Table 9.9 Pin States During Powerdown
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