11DMA Ports
11 – 7
BCR can be set to:
0 Allow program execution during BDMA
1 Inhibit program execution during BDMA transfers and cause a
context reset after transfer is complete
BMPAGE lets you select the starting page for BDMA transfer.
Note: Rebooting with BDMA Context Reset (BCR=1) is similar to a
Powerup Context Reset. For more details on processor states during reset
and reboot, see the System Interface chapter of this manual.
The BWCOUNT register lets you start a BDMA transfer by writing the
number of words for the transfer to this register. The count automatically
decrements as the transfer proceeds. When the count is zero (i.e. transfer
complete), the processor issues a BDMA interrupt. When MMAP and
BMODE are set to zero on boot, a value of 32 (decimal) is written to this
register directing the ADSP-2181 to load the first 32 locations of its
internal program memory.
Two useful control techniques using this register are:
• Poll the BWCOUNT register to determine when the DMA transfer is
complete (BWCOUNT=0), instead of waiting for the BDMA interrupt.
• Abort the DMA operation by writing a 1 to the BWCOUNT register and
poll to determine when the transfer is complete (BWCOUNT=0),
instead of waiting for the BDMA interrupt. (Note that the DMA transfer
is aborted, and cannot be resumed later.)
BMWAIT consists of bits 12, 13, and 14 of the Programmable Flag &
Composite Select Control Register. BMWAIT lets you select 0-7 waitstates
(each equal to a single instruction cycle) to apply to each byte memory
access. BMWAIT is set to 7 after a reboot.
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