13 Hardware Examples
13 – 14
To access one of the HIP registers, the 80C51 asserts ALE and outputs a
16-bit address, with the upper half on P2.0-2.7 and the lower half on
P0.0-0.7. The upper half is decoded to select the HIP via
HSEL
, and the
lower half selects the HIP register via HAD0-7. The ALE assertion causes
the HIP to latch the address so that the 8-bit data can then be transferred
on the HAD0-7 lines. The 80C51 asserts
WR
for a write or
RD
for a read.
In this example, the 80C51 reads and writes 8-bit data, so the ADSP-2111’s
HSIZE input is tied high. Only the lower eight bits of each HIP register are
used. HMD0 is tied low because the 80C51 uses separate read and write
strobes rather than a single Read/
Write
line. HMD1 is tied high because
the address and data use the same bus (time-multiplexed using ALE)
rather than separate buses.
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