Analog Devices adsp-2100 - Page 438

AInstruction Coding
A – 9
DREG Data Register codes
0 0 0 0 AX0
0 0 0 1 AX1
0 0 1 0 MX0
0 0 1 1 MX1
0 1 0 0 AY0
0 1 0 1 AY1
0 1 1 0 MY0
0 1 1 1 MY1
1 0 0 0 SI
1 0 0 1 SE
1 0 1 0 AR
1 0 1 1 MR0
1 1 0 0 MR1
1 1 0 1 MR2
1 1 1 0 SR0
1 1 1 1 SR1
DV Divisor codes for Slow Idle instruction ( IDLE (n) )
0 0 0 0 Normal Idle instruction (Divisor=0)
0 0 0 1 Divisor=16
0 0 1 0 Divisor=32
0 1 0 0 Divisor=64
1 0 0 0 Divisor=128
FIC FI condition code
1 latched FI is 1 “ FLAG_IN ”
0 latched FI is 0 “ NOT FLAG_IN ”
FO Control codes for Flag Output Pins (FO, FL0, FL1, FL2)
.
0 0 No change
0 1 Toggle
1 0 Reset
1 1 Set