Analog Devices adsp-2100 User Manual

Program Control3
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Because of the efficient stack and program sequencer, there is no latency
(beyond synchronization delay) when processing unmasked interrupts,
even when interrupting DO UNTIL loops. Nesting of interrupts allows
higher-priority interrupts to interrupt any lower-priority interrupt service
routines that may currently be executing, also with no additional latency.
The ADSP-2100 family processors include a secondary register set which
can be used to provide a fresh set of ALU, MAC, and Shifter registers
during interrupt servicing. This feature allows single-cycle context
switching. Use of the secondary registers is described in the “Mode Status
Register (MSTAT)” section of this chapter.
Interrupt Source Interrupt Vector Address
RESET startup 0x0000
IRQ2 0x0004 (highest priority)
SPORT0 Transmit 0x0008
SPORT0 Receive 0x000C
SPORT1 Transmit or
IRQ1 0x0010
SPORT1 Receive or
IRQ0 0x0014
Timer 0x0018 (lowest priority)
Table 3.2 ADSP-2101/2115 Interrupts & Interrupt Vector Addresses
Interrupt Source Interrupt Vector Address
RESET startup 0x0000
IRQ2 0x0004 (highest priority)
SPORT1 Transmit or
IRQ1 0x0010
SPORT1 Receive or
IRQ0 0x0014
Timer 0x0018 (lowest priority)
Table 3.3 ADSP-2105 Interrupts & Interrupt Vector Addresses
Interrupt Source Interrupt Vector Address
RESET startup 0x0000
IRQ2 0x0004 (highest priority)
HIP Write (from Host) 0x0008
HIP Read (to Host) 0x000C
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
SPORT1 Transmit or
IRQ1 0x0018
SPORT1 Receive or
IRQ0 0x001C
Timer 0x0020 (lowest priority)
Table 3.4 ADSP-2111 Interrupts & Interrupt Vector Addresses

Analog Devices adsp-2100 Specifications

General

Brand	Analog Devices
Model	adsp-2100
Category	Computer Hardware
Language	English