COBHAM GR740 - Page 455

GR740-UM-DS, Nov 2017, Version 1.7 455 www.cobham.com/gaisler
GR740
39.5.17 UART interface timing
The timing waveforms and timing parameters are shown in figure 71 and are defined in table 594.
Table 594.Timing parameters
Name Parameter Reference edge Min Max Unit
t
APBUART0
clock to output delay rising clk edge
0
1)
40
2)
ns
t
APBUART1
input to clock hold
rising clk edge
3)
--ns
t
APBUART2
input to clock setup
rising clk edge
3)
--ns
1)
Guaranteed by design, not tested.
2)
Verified by static timing analysis, not tested
3)
The _cstn and _rxd inputs are re-synchronized internally. These signals to not have to meet any setup or hold require-
ments.
Figure 71. Timing waveforms
t
APBUART0
_txd[], _rtsn[]
internal sys_clk
t
APBUART0
t
APBUART1
_rxd[], _ctsn[] t
APBUART2