(
(
(
(
/
506
EXPANSION
FEATURE CARD
82
(Page 2
of
2)
505,506
,-
+C4
S06
r-----------------------,
+C1
S07 I
Data Rate Clock
I
Rate
Set
16
Bit64K
~
~ft
REG
~"
I
REG
"
~
SOD
I
1
1
;J
2
2
-Bus
Out
6
J06
0
4
4
l....-
I 8
8
I
16
16
32 32
1
64
64
128 128
I
256 256
I
512 512
1024
1024
I
2048
2048
4096 4096
Clock
Preset
I
8192
8192
~
rr=B-
16384
16384
FL
32768
32768
~G
t-
OR
r-
+Rate
Gate
Clk
I
I-
CARRY
S
~
:
'--
~R
Symmetrical
-Adapter
Reset
INote4)
Clk Run
'--
O~
j-Ungated
OSC
I
Gate
...
+Transmit
Mode
T
1&
:
~
OSC Rst
I
Rev
Clk
~
~
"
OR
R
+Receive Mode
FL
'--
I
G
-Rcvd
Oata
I
s
I
I
R
N
1
'--
SBE,
R,t
or
Xmt
Mode
I
INote
1)
Start
Bit
~
1
1
tJ~'~
1
I
I
...
+5tart
Bit
Error
I
I
1&
~
I
I
I
AR-LD
I
I
INote
2)1
P04 +Receive
ModeINote6)r-
I
--"
-Data
Set
Ready CJ
t-
INote
2l
P13
+Com
Request
To
Send
1
~
+Com Mode
G1
SEL
f---
I
+SI
) Mode
INote
2)lp12
+Com Data
Term
Rdy
+Terminal Ready
:
;J
t----
INote
2)1
M03 +Com Xmit Data
1
--"
I
L
f---
r-
INote
2)1
B13 +SIO Data Term Rdy
~
2
I
c--
L
r-
INote 2)\ B12 +SIO Revd Line Sig Det
+SIO Req
To
Send
2
+Data Bit
\
I---
I
r-
INote
2)L02
+SIO Request
To
Send
~~
f::..---
-
I
"f---
!
INote
2)IG02
+SIO Xmit Data
u071
'---
I
-
~
+Ext
Horiz
Dr
1
Long Sp
I
1
Transmit
Timer
~a_
12 Bit
1000
I
\
Lg
Sp Decade
Ctr
A
~
1
I
..,......,
l-oRr-
co
PH
R
~A
I
\
~~~
e
R
1
Data Buffer INote 5)
I
PH
CD
I +Lg
Sp
Tmr
Carry
I
c
CARRY
...
" '
~
1&
1
I
R
I
INote3)
\
\
Notes:
L.
_________________________
~
1. Logic line leaves card
at
P06,
is
looped
on
the
board,
and
reenters 4. Four internal lines
of
the
data rate clock leave
the
card, are
the
card
at
P10. Either
point
may be tested with an oscilloscope as looped on
the
board,
and
return
to
the
card
at
the
following
a CE aid
to
determine clock frequency. pairs
of
pins: M11-M13, S04-U06, S09-S12, and S11-U11.
2. Acceptable voltage level range: Up +3.0V
to
+25.0V, down
-3.0V
5. The 'start bit
error'latch
is
on during
data
transmission only
to
-25.0V.
while running
CE
diagnostic programs; otherwise, normal data
3.
Four internal lines
of
the
long space
timer
leave
the
card, are looped transfer
is
through
the
transmit data buffer.
on
the
board, and return
to
the
card
at
the
following pairs of pins: 6. This line used by TRAP tester only.
G03-G04, J04-J05, M10-S05
and
S13-U13.
Logics
5-17
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