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Fetch
and
Store Microinstructions:
LDBI, Rx, Ry, M (op code 6): The byte of data at the
storage location designated by the address register (Ry)
is
read into the low order byte
of
the data register (Rx).
Then the address in the address register (Ry)
is
modified
as
shown
by
the following chart:
Modifier
o
1
2
3
4
5
6
7
Greater
than 7
Plus 1
is
added
to
the contents of Ry.
Plus 2
is
added
to
the contents of Ry.
Plus
3
is
added
to
the contents of Ry.
Plus
4
is
added
to
the contents of Ry.
Minus
1
is
subtracted from the contents of Ry.
Minus
2
is
subtracted from the contents
of
Ry.
Minus
3
is
subtracted from the contents
of
Ry.
Minus
4
is
subtracted from the contents
of
Ry.
Ry
-
No
change.
LDHD
Rx, ADDRESS (op code 2): A halfword from the
location defined by the halfword address
is
read into the
data register (Rx).
LDHI
Rx, Ry, M (op code
D):
The halfword located at
the address in the address register
Ry
is
read into the data
register (Rx). Then the address
in
the address register (Ry)
is
modified
as
shown
by
the chart following the
LDBI
microi nstruction.
STBI
Rx, Ry, M (op code 7): The low order byte
in
the
data register (Rx)
is
stored
in
the location designated by
the address register (Ry). Then the address
in
the address
register
is
modified
as
shown by the chart following the
LDBI
microinstruction.
~'THD
Rx, ADDRESS (op code 3): The halfword in
the
data register (Rx)
is
stored
in
the location at the halfword
address defined by bits 8-15
of
the
microinstruction.
STHI
Rx, Ry, M (op code 5): The halfword
in
the data
register (Rx)
is
stored at the location specified by the
address register (Ry). Then the address register (Ry)
is
modified
as
indicated
in
the chart following the
LDBI
microinstruction.
Register Operation Microinstructions:
HTL
Rx,
Ry
(op code 0): The high order byte
of
regrste~
Ry
is
moved
to
the low order byte
of
register Rx. Register
Ry
is
not changed unless
Ry
and
Rx
are designated
as
the
same register.
L TH Rx,
Ry
(op code 0): The low order byte
of
register
Ry
is
moved
to
the high order byte of register Rx. Register
Ry
is
not
changed unless Ry and
Rx
are designated
as
the
same register.
MOVE
Rx,
Ry
(op code 0): The halfword
in
register
Ry
is
moved
to
register Rx and Ry
is
not
changed.
MVM1
Rx,
Ry
(op code 0): The halfword
in
register
Ry
is
moved
to
register Rx and the Rx
is
decremented
by
1.
Register
Ry
is
not
changed.
MVM2
Rx,
Ry
(op code 0): The halfword
in
register
Ry
is
moved
to
register Rx and
then
Rx
is
decremented by 2.
Register
Ry
is
not
changed.
MVP1
Rx,
Ry
(op code 0): The halfword
in
register
Ry
is
moved
to
register
Rx
and then.
Rx
is
incremented by one.
Register
Ry
is
not
changed.
MVP2
Rx, Ry (op code 0): The halfword in register Ry
is
moved
to
register
Rx
and then
Rx
is
incremented by 2.
Register
Ry
is
not
changed.
Logical Register Microinstructions:
AND
Rx,
Ry
(op code 0): The low order byte
of
register
Ry
is
ANDed with
the
low order byte
of
register Rx and
the results are placed into the low order byte of Rx.
CLRI
Rx,
MASK
(op code 9): The 1 bits
in
the mask
(8-15 of the microinstruction) set
the
corresponding bits
in
the low order byte of register Rx
to
O.
Zeros
in
the
mask have no effect on register Rx.
EMIT
Rx, DATA (op code 8): The data (bits 8-15 of the
instruction)
is
put into the low order byte of register Rx.
ORB Rx,
Ry
(op code 0): The low order byte
of
register
Ry
is
ORed with
the
low order byte
of
Rx
and
the
results
are
placed into the low order byte
of
Rx .
Microinstructions C-15
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