iSeries architecture: Fundamental strength of the IBM ^ i5 and iSeries 19
Draft Document for Review October 18, 2004 5486AdvTech.fm
POWER4
POWER4 cannot be considered only a chip, but rather an
architecture of how a set of chips is designed together to
build a system. As such, POWER4 can be considered a
technology in its own right. The interconnect topology,
referred to as a
Distributed Switch, is new to the industry
with POWER4. In that light, systems are built by
interconnecting POWER4 chips to form up to 32-way
symmetric multiprocessors. The reliability, availability, and
serviceability (RAS) design incorporated into POWER4 is
pervasive throughout the system and is as much a part of the design. POWER4
is the chip technology used in the iSeries Model 825, 870, and 890.
The POWER4 design can handle a varied and robust set of workloads. This is
especially important as the on demand business world evolves and data
intensive demands on systems merge with commercial requirements. The need
to satisfy high performance computing requirements with its historical high
bandwidth demands and commercial requirements, along with data sharing and
SMP scaling requirements dictate a single design to address both environments.
POWER5
POWER5 technology is the ninth generation of 64-bit
architecture. Although the hardware is based on POWER4,
POWER5 is much more than just an improvement in
processor or chip design. It is a complete architectural
change, creating a much more efficient superscalar
processor complex. For example, the high performance
distributed switch is enhanced. POWER5 technology is
implemented in the Eserver i5 Model 520, 550, 570, and
595.
As with previous hardware technology, POWER5 technology-based processors
have two load/store, two arithmetic, and one branch unit. The
processor complex
design is built in such a way that it can most efficiently execute multiple
instruction streams concurrently. With simultaneous multithreading (SMT) active,
instructions of two different threads can be issued per single cycle.
The POWER5 concept is a step further into autonomic computing. Several
enhanced reliability and availability enhancements are implemented. Along with
increased redundant components, it incorporates new technological high
standards, such as special ways to reduce junction temperatures to reach a high
level of availability. The full system design approach is required to maintain
balanced utilization of hardware resources and high availability of the new
Eserver i5 systems.
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