5486AdvTech.fm Draft Document for Review October 18, 2004
16 IBM Eserver i5 and iSeries System Handbook
programs execute on POWER5 microprocessors, movement of data is handled
by high performance I/O adapters and I/O processors. Data moves between I/O
towers and to Integrated xSeries Adapter PC servers across HSL at
2 GB/second and storage area network (SAN) disk and tape devices are
supported at 2 Gb/second over Fibre Channel.
The multichip modules (MCMs) contain eight processors each. In such an MCM,
there are four physical copper SOI chips with two processor cores. Each core is
capable of running symetric multi-threading that to the operating system looks
like two separete processors. Each chip contains 276 million transistors forming
two processors running at a speed in excess of 1.5GHz. The 8-way MCM is the
building block for the system. It is only available with four chips, each with its
attached L3 cache. A single processor on a chip has all of the L2 and L3 cache
resources attached to the module (144 MB per MCM).
On an iSeries Model 595, a 64-way symmetric multiprocessing (SMP)
configuration is implemented with eight MCMs, with each MCM containing four
dual core POWER5 chips running at speeds greater than 1.5 GHz.
A single large iSeries configuration can have well over 650 processors. The main
system processor complex (can be comprised of 64 separate processors) can
encounter a request for data to be read from or written to any I/O device. That
request for data is delegated to the particular microprocessor dedicated to that
I/O device. Meanwhile, the main system processor continues executing another
application program. Nanoseconds (10
-9
second) is the unit of time used to
measure main storage access times. I/O operations are measured in
milliseconds (10
-3
second).
Technology in stride
The iSeries server delivers tremendous capacity growth in its product line. The
iSeries Layer (also known as Technology Independent Machine Interface) has
made it possible to completely change the underlying hardware with minimum, if
any, impact to iSeries applications. TIMI helps condition the iSeries to bring new
technology to market.
The first AS/400e models based on the 64-bit RISC PowerPC® AS processors
were announced in June 1995. In 1997, the 12-way AS/400e system was
delivered using Power PCA35 microprocessors. Known as Apache technology,
the Power PCA35 microprocessors provided a growth of 4.6 times. In September
1998, a 12-way AS/400e system was delivered using the Power PCA50
microprocessor. Known as code name Northstar, the Power PCA50
microprocessors nearly doubled the high-end capacity. This set of processors
provided the fourth generation since the AS/400 system’s inception in 1988 with
64-bit AS/400 Power PCs microprocessors. The latest generation of POWER5
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