7: BASIC INSTRUCTIONS
7-22 OPENNET CONTROLLER USER’S MANUAL
Reverse Shift Register (SFRN)
For reverse shifting, use the SFRN instruction. When SFRN instructions are programmed, two addresses are always
required. The SFRN instructions are entered, followed by a shift register number selected from appropriate operand num-
bers. The shift register number corresponds to the lowest bit number in a string. The number of bits is the second required
address after the SFRN instructions.
The SFRN instruction requires three inputs. The reverse shift register circuit must be programmed in the following order:
reset input, pulse input, data input, and the SFRN instruction, followed by the last bit and the number of bits.
Structural Diagram
I2
I0
R20
Reset
Data
I1
Pulse
R21 R22 R23
Shift Direction
Last Bit: R20 # of Bits: 7
R24 R25 R26
Note: Output is initiated only for those bits highlighted in bold print.
Note: When power is turned off, the statuses of all shift register bits are normally cleared. It is also possible to main-
tain the statuses of shift register bits by using the Function Area Settings as required. See page 5-3.
Note: SFR(N) shifting flag special internal relay M8012 is turned on when the CPU is powered down while data shifting
is in progress. See page 6-10.
• The last bit status output can be programmed
directly after the SFRN instruction. In this exam-
ple, the status of bit R20 is read to output Q0.
• Each bit can be loaded using the LOD R# instruc-
tions.
• For details of reset, pulse, and data inputs, see
page 7-20.
Ladder Diagram
Last Bit: R0 to R255
# of Bits: 1 to 256
I0
I1
SFRN R20
7
I2
Reset
Pulse
Data
R21
Rung 2
Rung 1
Last Bit
# of Bits
R23
R25
Prgm Adrs Instruction Data
Rung 1 0
1
2
3
4
5
LOD
LOD
LOD
SFRN
OUT
I0
I1
I2
R20
7
Q0
Rung 2 6
7
8
9
10
11
LOD
OUT
LOD
OUT
LOD
OUT
R21
Q1
R23
Q2
R25
Q3
Program List
Caution
• When using WindLDR Ver 3, any instruction cannot be
programmed immediately above and below the SFRN
instruction. To program other instructions, start a new
rung. If an instruction is entered above or below the
SFRN instruction in the same rung, the program is not
compiled correctly.
Q0
Q3
Q1
Q2
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