Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
E-18
To different privilege level (within task) 86 g, h, j, k,
r
From 286 task to 286 TSS 285 g, h, j, k,
r
From 286 task to Intel386 SX CPU TSS 318 g, h, j, k,
r
From 286 task to virtual 8086 task 267 g, h, j, k,
r
From 286 task to virtual 8086 mode (within task) 113
From Intel386 SX CPU task to 286 TSS 324 g, h, j, k,
r
From Intel386 SX CPU task to Intel386 SX CPU TSS 328 g, h, j, k,
r
From Intel386 SX CPU task to virtual 8086 task 377 g, h, j, k,
r
From Intel386 SX CPU task to virtual 8086 mode (within task) 113
PROCESSOR CONTROL INSTRUCTIONS
HLT = Halt 1 1 1 1 0 1 0 0 7 7 l
MOV = Move to and from control/debug/test registers
CR0/CR2/CR3 from
register
0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 1 e e e reg
10/4/5 10/4/5 l
register from CR0-3 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 e e e reg 6 6 l
DR0-3 from register 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 e e e reg 22 22 l
DR6-7 from register 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 e e e reg 16 16 l
register from DR6-7 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 e e e reg 14 14 l
register from DR0-3 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 e e e reg 22 22 l
TR6-7 from register 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1 e e e reg 12 12 l
register from TR6-7 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 e e e reg 12 12 l
NOP = No operation 1 0 0 1 0 0 0 0 3 3
WAIT = Wait until BUSY#
pin is negated
1 0 0 1 1 0 1 1
66
PROCESSOR EXTENSION INSTRUCTIONS
Processor Extension
Escape
1 1 0 1 1 T T T mod L L L r/m See
Intel387
SX
datashe
et for
clock
counts
h
TTT and LLL bits are opcode
information for coprocessor
Table E-1. Instruction Set Summary (Sheet 17 of 19)
Instruction Format
Clock Count Notes
Real
Ad-
dress
Mode
or
Virtual
8086
Mode
Pro-
tected
Virtual
Ad-
dress
Mode
Real
Ad-
dress
Mode
or
Virtual
8086
Mode
Pro-
tected
Virtual
Ad-
dress
Mode
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