Intel 855GME User Manual

6
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
5.4.3.3 Clock Length Package Table...............................................................130
5.4.4 Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0] ...............................................130
5.4.4.1 Data Bus Topology ..............................................................................131
5.4.4.2 SDQS to Clock Length Matching Requirements..................................133
5.4.4.3 Data to Strobe Length Matching Requirements...................................134
5.4.4.4 SDQ to SDQS Mapping.......................................................................135
5.4.4.5 SDQ/SDQS Signal Package Lengths ..................................................136
5.4.5 Control Signals – SCKE[3:0], SCS[3:0]# .............................................................138
5.4.5.1 Control Signal Routing Topology .........................................................139
5.4.5.2 Control Signal Routing Guidelines.......................................................140
5.4.5.3 Control to Clock Length Matching Requirements ................................140
5.4.5.4 Control Group Package Length Table .................................................142
5.4.6 Command Signals – SMA[12:6,3,0], SBA[1:0],
SRAS#, SCAS#, SWE#.......................................................................................142
5.4.6.1 Command Signal Routing Topology ....................................................142
5.4.6.2 Command Topology Routing Guidelines .............................................143
5.4.6.3 Command Topology Length Matching Requirements..........................144
5.4.6.4 Command Group Package Length Table ............................................146
5.4.7 CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] ......................................................146
5.4.7.1 CPC Signal Routing Topology .............................................................147
5.4.7.2 CPC Signal Routing Guidelines...........................................................148
5.4.7.3 CPC to Clock Length Matching Requirements ....................................148
5.4.7.4 CPC Group Package Length Table .....................................................150
5.4.8 Feedback – RCVENOUT#, RCVENIN#...............................................................150
5.5 ECC Guidelines................................................................................................................150
5.5.1 GMCH ECC Functionality....................................................................................150
5.5.2 DRAM Clock Flexibility ........................................................................................151
6 Integrated Graphics Display Port.............................................................................................153
6.1 Analog RGB/CRT Guidelines ...........................................................................................153
6.1.1 RAMDAC/Display Interface .................................................................................153
6.1.2 Reference Resistor (RSET).................................................................................153
6.1.3 RAMDAC Board Design Guidelines ....................................................................154
6.1.4 DAC Routing Guidelines......................................................................................155
6.1.5 DAC Power Requirements...................................................................................157
6.1.6 HSYNC and VSYNC Design Considerations.......................................................158
6.1.7 DDC and I
2
C Design Considerations...................................................................158
6.2 LVDS Transmitter Interface..............................................................................................158
6.2.1 Length Matching Constraints...............................................................................159
6.2.1.1 Package Length Compensation...........................................................159
6.2.2 LVDS Routing Guidelines....................................................................................160
6.3 Digital Video Out Port.......................................................................................................161
6.3.1 DVO Interface Signal Groups ..............................................................................162
6.3.1.1 DVO/I2C to AGP Pin Mapping.............................................................162
6.3.2 DVOB and DVOC Port Interface Routing Guidelines ..........................................163
6.3.2.1 Length Mismatch Requirements ..........................................................163
6.3.2.2 Package Length Compensation...........................................................164
6.3.2.3 DVOB and DVOC Routing Guidelines.................................................165
6.3.2.4 DVOB and DVOC Port Termination.....................................................166
6.3.3 DVOB and DVOC Assumptions, Definitions, and Specifications.........................167
6.3.4 DVOB and DVOC Simulation Method .................................................................167
6.4 DVOB and DVOC Port Flexible (Modular) Design............................................................168

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English