Intel 855GME User Manual

7
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
6.4.1 DVOB and DVOC Module Design .......................................................................168
6.4.1.1 Generic Connector Model ....................................................................169
6.5 DVO GMBUS and DDC Interface Considerations ............................................................170
6.5.1 Leaving the GMCH DVOB or DVOC Port Unconnected......................................171
6.6 Miscellaneous Input Signals and Voltage Reference .......................................................171
7 AGP Port Design Guidelines ....................................................................................................173
7.1 AGP Interface ...................................................................................................................173
7.1.1 AGP 2.0 ...............................................................................................................173
7.1.2 AGP Interface Signal Groups ..............................................................................174
7.2 AGP Routing Guidelines...................................................................................................175
7.2.1 1x Timing Domain Routing Guidelines.................................................................175
7.2.1.1 Trace Length Requirements for AGP 1X .............................................175
7.2.1.2 Trace Spacing Requirements ..............................................................175
7.2.1.3 Trace Length Mismatch .......................................................................175
7.2.2 2x/4x Timing Domain Routing Guidelines............................................................175
7.2.2.1 Trace Length Requirements for AGP 2X/4X........................................175
7.2.2.2 Trace Spacing Requirements ..............................................................176
7.2.2.3 Trace Length Mismatch Requirements ................................................177
7.2.3 AGP Clock Skew .................................................................................................177
7.2.4 AGP Signal Noise Decoupling Guidelines...........................................................178
7.2.5 AGP Interface Package Lengths .........................................................................178
7.2.6 AGP Routing Ground Reference .........................................................................179
7.2.7 Pull-Ups ...............................................................................................................180
7.2.8 AGP VDDQ and VCC ..........................................................................................181
7.2.9 VREF Generation for AGP 2.0 (2X and 4X) ........................................................181
7.2.9.1 1.5 V AGP Interface (2X/4X)................................................................181
7.2.10 AGP Compensation.............................................................................................181
7.2.11 PM_SUS_CLK/AGP_PIPE# Design Consideration.............................................181
8Hub Interface..............................................................................................................................183
8.1 8-Bit Hub Interface Routing Guidelines. ...........................................................................183
8.1.1 8-Bit Hub Interface Data Signals .........................................................................183
8.1.2 8-Bit Hub Interface Signal Referencing ...............................................................184
8.1.3 8-Bit Hub Interface Strobe Signals ......................................................................184
8.1.4 8-bit Hub Interface HIREF and HI_VSWING Generation/Distribution..................184
8.1.4.1 GMCH Single Generated Voltage Reference Divider Circuit...............187
8.1.4.2 Separate GMCH Voltage Divider Circuits for HLVREF and PSWING .188
8.1.5 Hub Interface Compensation...............................................................................189
8.1.6 8-Bit Hub Interface Decoupling Guidelines..........................................................189
8.1.7 Terminating HI_11 If Not Used ............................................................................189
9Intel
®
6300ESB Design Guidelines ..........................................................................................191
9.1 Serial ATA Interface..........................................................................................................191
9.1.1 Layout Guidelines ................................................................................................191
9.1.1.1 General Routing and Placement..........................................................191
9.1.1.2 Serial ATA Trace Separation ...............................................................191
9.1.1.3 Serial ATA Trace Length Pair Matching...............................................192
9.1.1.4 Serial ATA Trace Length Guidelines....................................................192
9.1.1.5 SATA BIAS Connections .....................................................................192
9.1.1.6 SATALED# Implementation.................................................................193

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English