Motorola MC68HC908AB32 User Manual

System Integration Module (SIM)
SIM Registers
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA System Integration Module (SIM) 129
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST
)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
8.8.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Address: $FE03
Bit 7 654321Bit 0
Read:
BCFE RRRRRRR
Write:
Reset: 0
R = Reserved
Figure 8-19. SIM Break Flag Control Register (SBFCR)

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English