Timer Interface Module B (TIMB)
Interrupts
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Timer Interface Module B (TIMB) 207
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMB channel 2 registers (TBCH2H:TBCH2L)
initially control the PWM output. TIMB channel 2 status and control
register (TBSC2) controls and monitors the PWM signal from the linked
channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See 12.10.4 TIMB
Channel Status and Control Registers.
12.6 Interrupts
The following TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value rolls over to $0000 after matching the value in the
TIMB counter modulo registers. The TIMB overflow interrupt
enable bit, TOIE, enables TIMB overflow CPU interrupt requests.
TOF and TOIE are in the TIMB status and control register.
• TIMB channel flags (CH3F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE= 1. CHxF and CHxIE are in the TIMB
channel x status and control register.
12.7 Low-Power Modes
The WAIT and STOP instructions puts the MCU in low-power-
consumption standby modes.
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