Timer Interface Module B (TIMB)
Technical Data MC68HC908AB32 — Rev. 1.0
212 Timer Interface Module B (TIMB) MOTOROLA
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/TBCLK pin or one of the
seven prescaler outputs as the input to the TIMB counter as
Table 12-2 shows. Reset clears the PS[2:0] bits.
12.10.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE:
If you read TBCNTH during a break interrupt, be sure to unlatch
TBCNTL by reading TBCNTL before exiting the break interrupt.
Otherwise, TBCNTL retains the value latched during the break.
Table 12-2. Prescaler Selection
PS2 PS1 PS0 TIM Clock Source
0 0 0 Internal Bus Clock ÷1
0 0 1 Internal Bus Clock ÷ 2
0 1 0 Internal Bus Clock ÷ 4
0 1 1 Internal Bus Clock ÷ 8
1 0 0 Internal Bus Clock ÷ 16
1 0 1 Internal Bus Clock ÷ 32
1 1 0 Internal Bus Clock ÷ 64
1 1 1 PTD4/TBCLK
Address: $0041
Bit 7 654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 00000000
=
Unimplemented
Figure 12-5. TIMB Counter Register High (TBCNTH)
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